Re: [Qemu-arm] [PATCH V2 3/5] target-arm: Add support for PMU register PMXEVCNTR_EL0

[Peter Maydell]

On 31 January 2017 at 15:15, Wei Huang <address@hidden> wrote:
> To make PMU register support complete, this patch adds support for
> PMXEVCNTR_EL0.
>
> Signed-off-by: Wei Huang <address@hidden>
> ---
>  target/arm/helper.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index c8620d9..6b8460a 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1255,6 +1255,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>      { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 
> 2,
>        .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
>        .accessfn = pmreg_access },
> +    { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
> +      .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
> +      .accessfn = pmreg_access },

We don't need to do this, because we're already spec-compliant.
Since we only support the cycle counter, accesses to PMXEVCNTR
are always CONSTRAINED UNPREDICTABLE and "accesses UNDEF" is
a permitted choice, which is what we do at the moment.
('Accesses are RAZ/WI' are also a permitted choice.)

Is there a reason you've opted for the RAZ/WI here?

thanks
-- PMM