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Re: [Qemu-arm] [Qemu-devel] [PATCH v2 01/18] hw/intc/arm_gicv3: Add exte
From: |
Alistair Francis |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v2 01/18] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ |
Date: |
Tue, 17 Jan 2017 13:49:35 -0800 |
On Mon, Jan 9, 2017 at 8:05 AM, Peter Maydell <address@hidden> wrote:
> Augment the GICv3's QOM device interface by adding two
> new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to
> each CPU.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Thanks,
Alistair
> ---
> include/hw/intc/arm_gicv3_common.h | 2 ++
> hw/intc/arm_gicv3_common.c | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/include/hw/intc/arm_gicv3_common.h
> b/include/hw/intc/arm_gicv3_common.h
> index 341a311..beb2c77 100644
> --- a/include/hw/intc/arm_gicv3_common.h
> +++ b/include/hw/intc/arm_gicv3_common.h
> @@ -145,6 +145,8 @@ struct GICv3CPUState {
> CPUState *cpu;
> qemu_irq parent_irq;
> qemu_irq parent_fiq;
> + qemu_irq parent_virq;
> + qemu_irq parent_vfiq;
>
> /* Redistributor */
> uint32_t level; /* Current IRQ level */
> diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
> index 0aa9b9c..0ee67a4 100644
> --- a/hw/intc/arm_gicv3_common.c
> +++ b/hw/intc/arm_gicv3_common.c
> @@ -126,6 +126,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s,
> qemu_irq_handler handler,
> for (i = 0; i < s->num_cpu; i++) {
> sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
> }
> + for (i = 0; i < s->num_cpu; i++) {
> + sysbus_init_irq(sbd, &s->cpu[i].parent_virq);
> + }
> + for (i = 0; i < s->num_cpu; i++) {
> + sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
> + }
>
> memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
> "gicv3_dist", 0x10000);
> --
> 2.7.4
>
>
- [Qemu-arm] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 09/18] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 14/18] hw/arm/virt: Support using SMC for PSCI, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 11/18] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 01/18] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2017/01/09
- Re: [Qemu-arm] [Qemu-devel] [PATCH v2 01/18] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ,
Alistair Francis <=
- [Qemu-arm] [PATCH v2 18/18] hw/arm/virt: Add board property to enable EL2, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 15/18] hw/arm/virt-acpi-build: use SMC if booting in EL2, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 17/18] target-arm: Enable EL2 feature bit on A53 and A57, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 07/18] hw/intc/gicv3: Add data fields for virtualization support, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 06/18] hw/intc/gicv3: Add defines for ICH system register fields, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 08/18] hw/intc/arm_gicv3: Add accessors for ICH_ system registers, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU, Peter Maydell, 2017/01/09