[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-arm] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenanc
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-arm] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU |
Date: |
Tue, 10 Jan 2017 17:42:36 +0100 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Mon, Jan 09, 2017 at 04:05:10PM +0000, Peter Maydell wrote:
> Wire the new VIRQ, VFIQ and maintenance interrupt lines from the
> GIC to each CPU.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> include/hw/arm/virt.h | 2 ++
> hw/arm/virt.c | 14 +++++++++++---
> 2 files changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
> index eb1c63d..b8a19ec 100644
> --- a/include/hw/arm/virt.h
> +++ b/include/hw/arm/virt.h
> @@ -39,6 +39,8 @@
> #define NUM_GICV2M_SPIS 64
> #define NUM_VIRTIO_TRANSPORTS 32
>
> +#define ARCH_GICV3_MAINT_IRQ 9
> +
> #define ARCH_TIMER_VIRT_IRQ 11
> #define ARCH_TIMER_S_EL1_IRQ 13
> #define ARCH_TIMER_NS_EL1_IRQ 14
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 7a03f84..b31d302 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -547,9 +547,9 @@ static void create_gic(VirtMachineState *vms, qemu_irq
> *pic)
> sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
> }
>
> - /* Wire the outputs from each CPU's generic timer to the
> - * appropriate GIC PPI inputs, and the GIC's IRQ output to
> - * the CPU's IRQ input.
> + /* Wire the outputs from each CPU's generic timer and the GICv3
> + * maintenance interrupt signal to the appropriate GIC PPI inputs,
> + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
> */
> for (i = 0; i < smp_cpus; i++) {
> DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
> @@ -571,9 +571,17 @@ static void create_gic(VirtMachineState *vms, qemu_irq
> *pic)
> ppibase +
> timer_irq[irq]));
> }
>
> + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
> + qdev_get_gpio_in(gicdev, ppibase
> + +
> ARCH_GICV3_MAINT_IRQ));
> +
> sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev,
> ARM_CPU_IRQ));
> sysbus_connect_irq(gicbusdev, i + smp_cpus,
> qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
> + sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
> + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
> + sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
I thought there was an error here first (i.e i * smp_cpus + 3).
The code is correct but could have perhaps been more readable with named irqs.
Anyway, it looks correct:
Reviewed-by: Edgar E. Iglesias <address@hidden>
> + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
> }
>
> for (i = 0; i < NUM_IRQS; i++) {
> --
> 2.7.4
>
- [Qemu-arm] [PATCH v2 18/18] hw/arm/virt: Add board property to enable EL2, (continued)
- [Qemu-arm] [PATCH v2 18/18] hw/arm/virt: Add board property to enable EL2, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 15/18] hw/arm/virt-acpi-build: use SMC if booting in EL2, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 17/18] target-arm: Enable EL2 feature bit on A53 and A57, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 07/18] hw/intc/gicv3: Add data fields for virtualization support, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 06/18] hw/intc/gicv3: Add defines for ICH system register fields, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 08/18] hw/intc/arm_gicv3: Add accessors for ICH_ system registers, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU, Peter Maydell, 2017/01/09
- Re: [Qemu-arm] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU,
Edgar E. Iglesias <=
- [Qemu-arm] [PATCH v2 03/18] target-arm: Expose output GPIO line for VCPU maintenance interrupt, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 05/18] target-arm: Add ARMCPU fields for GIC CPU i/f config, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 02/18] hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 12/18] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(), Peter Maydell, 2017/01/09
- [Qemu-arm] [PATCH v2 16/18] target/arm/psci.c: If EL2 implemented, start CPUs in EL2, Peter Maydell, 2017/01/09