[lwip-users] Problem running lwip on cortex M7 with D cache enabled

[Jochen Strohbeck]

Hello,

I'm using lwip 1.4.1 and FreeRTOS on a SAME70 custom board with success
if D-cache is disabled. If I enable the D-cache no more packets are
received. If I place the RX descriptor into a non-cacheable region I get
packets again but the received data is corrupt. Here is the lwip output:

 Checksum (0xa5fd) failed, IP packet dropped.
 IP (len 96) is longer than pbuf (len 50), IP packet dropped.

I understand that I have to move the receive (and send) buffers which
are used by the GMAC DMA to a non-cacheable region too. And here is
where my problem starts. In my understanding these buffers are by
default in an lwip memory pool. If I simply place the entire memory pool
to non-cacheable region the CPU hangs up. I guess this is due to the
D-cache requirements that the (GMAC) DMA buffer must be aligned to
32bytes but I don't know how to modify the lwip code in such a way that
the receive buffer (pbuf->payload?) is 32byte aligned. The other (and
better?) way would be to separate the receive buffer (or pbuf->payload)
from the lwip memory pool so I can place it everywhere I want but I
don't know how to manage this. Probably there is a better way to do so
in lwip ?

Any help is welcome.