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From: | Sreenath S |
Subject: | [lwip-users] How to use Xilinx-lwIP with an external MAC core. [ MAC + PHY chip SMSC 91C111 ] |
Date: | Tue, 14 Apr 2009 15:39:09 +0530 |
Hi All,
I want to use lwIP with the external MAC + PHY chip [ SMSC 91C111 ] in my board.
Now I am able to access all SMSC 91C111 registers using epc (External Peripheral Controller).
However when I add lwIP support in the "Software Platform settings" and try to compile, I gets the following error,
ERROR:MDT - issued from TCL procedure "::sw_lwip_v3_00_a::lwip_drc" line 12
lwip () - No Ethernet MAC cores are addressable from processor microblaze_0.
lwIP requires atleast one EMAC (xps_ethernetlite | xps_ll_temac) core.
So the LwIP library come with the Xilinx EDK only works with Xilinx IP cores (emac).
Is there a possibility of using lwIP with external MAC core (external MAC controller chip). ?
In order to use the Xilinx EMAC IP cores, I require the support of external PHY chip.
However in my case, ethernet pins coming out are routed through SMSC 91C111.
So I don't have any other option other than use SMSC 91C111 along with lwIP library.
Please find the MHS and MSS files below for further reference and please suggest a solution.
Thanks & Regards,
Sreenath
MHS
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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 9.2.02 Build EDK_Jm_SP2.3
# Tue Apr 07 12:06:04 2009
# Target Board: Custom
# Family: virtex5
# Device: xc5vlx110
# Package: ff1760
# Speed Grade: -1
# Processor: microblaze_0
# System clock frequency: 100.00 MHz
# On Chip Memory : 64 KB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT xps_epc_ethernet_PRH_Data_pin = xps_epc_ethernet_PRH_Data, DIR = IO, VEC = [0:31]
PORT xps_epc_ethernet_PRH_Wr_n_pin = xps_epc_ethernet_PRH_Wr_n, DIR = O
PORT xps_epc_ethernet_PRH_Rd_n_pin = xps_epc_ethernet_PRH_Rd_n, DIR = O
PORT xps_epc_ethernet_PRH_BE_pin = xps_epc_ethernet_PRH_BE, DIR = O, VEC = [0:3]
PORT xps_epc_ethernet_PRH_ADS_pin = xps_epc_ethernet_PRH_ADS, DIR = O
PORT xps_epc_ethernet_PRH_Addr_pin = xps_epc_ethernet_PRH_Addr, DIR = O, VEC = [0:15]
PORT xps_epc_ethernet_PRH_CS_n_pin = xps_epc_ethernet_PRH_CS_n, DIR = O, VEC = [0:0]
PORT util_vector_logic_ethernet_BE_Res_pin = util_vector_logic_ethernet_BE_Res, DIR = O, VEC = [0:3]
PORT util_vector_logic_ethernet_DATACS_Res_pin = util_vector_logic_ethernet_DATACS_Res, DIR = O, VEC = [0:0]
PORT util_vector_logic_ethernet_RESET_Res_pin = util_vector_logic_ethernet_RESET_Res, DIR = O, VEC = [0:0]
PORT util_vector_logic_ethernet_AEN_Res_pin = util_vector_logic_ethernet_AEN_Res, DIR = O, VEC = [0:0]
PORT util_vector_logic_ethernet_ADS_Res_pin = util_vector_logic_ethernet_ADS_Res, DIR = O, VEC = [0:0]
PORT xps_epc_ethernet_PRH_Rdy_pin = xps_epc_ethernet_PRH_Rdy, DIR = I, VEC = [0:0]
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER HW_VER = 7.00.b
PARAMETER C_DEBUG_ENABLED = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
PORT MB_RESET = mb_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.00.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN xps_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.a
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 1
PARAMETER C_USE_PARITY = 1
PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_RX
PORT TX = fpga_0_RS232_TX
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PORT CLKOUT0 = sys_clk_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
END
BEGIN xps_epc
PARAMETER INSTANCE = xps_epc_ethernet
PARAMETER HW_VER = 1.00.a
PARAMETER C_PRH0_ADDR_TSU = 12000
PARAMETER C_PRH0_ADDR_TH = 12000
PARAMETER C_PRH0_ADS_WIDTH = 20000
PARAMETER C_PRH0_CSN_TSU = 12000
PARAMETER C_PRH0_CSN_TH = 12000
PARAMETER C_PRH0_WRN_WIDTH = 30000
PARAMETER C_PRH0_WR_CYCLE = 100000
PARAMETER C_PRH0_DATA_TSU = 20000
PARAMETER C_PRH0_DATA_TH = 10000
PARAMETER C_PRH0_RDN_WIDTH = 30000
PARAMETER C_PRH0_RD_CYCLE = 100000
PARAMETER C_PRH0_DATA_TOUT = 10000
PARAMETER C_PRH0_DATA_TINV = 20000
PARAMETER C_PRH0_RDY_TOUT = 20000
PARAMETER C_PRH0_RDY_WIDTH = 100000
PARAMETER C_PRH_MAX_AWIDTH = 16
PARAMETER C_PRH0_AWIDTH = 16
PARAMETER C_PRH0_SYNC = 0
PARAMETER C_PRH0_BASEADDR = 0x84500000
PARAMETER C_PRH0_HIGHADDR = 0x8457ffff
BUS_INTERFACE SPLB = mb_plb
PORT PRH_Data = xps_epc_ethernet_PRH_Data
PORT PRH_Wr_n = xps_epc_ethernet_PRH_Wr_n
PORT PRH_Rd_n = xps_epc_ethernet_PRH_Rd_n
PORT PRH_BE = xps_epc_ethernet_PRH_BE
PORT PRH_ADS = xps_epc_ethernet_PRH_ADS
PORT PRH_Addr = xps_epc_ethernet_PRH_Addr
PORT PRH_CS_n = xps_epc_ethernet_PRH_CS_n
PORT PRH_Rdy = xps_epc_ethernet_PRH_Rdy
END
BEGIN util_vector_logic
PARAMETER INSTANCE = util_vector_logic_ethernet_BE
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPERATION = not
PARAMETER C_SIZE = 4
PORT Op1 = xps_epc_ethernet_PRH_BE
PORT Res = util_vector_logic_ethernet_BE_Res
END
BEGIN util_vector_logic
PARAMETER INSTANCE = util_vector_logic_ethernet_DATACS
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPERATION = or
PARAMETER C_SIZE = 1
PORT Op1 = net_vcc
PORT Op2 = net_vcc
PORT Res = util_vector_logic_ethernet_DATACS_Res
END
BEGIN util_vector_logic
PARAMETER INSTANCE = util_vector_logic_ethernet_RESET
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPERATION = or
PARAMETER C_SIZE = 1
PORT Op1 = mb_reset
PORT Op2 = mb_reset
PORT Res = util_vector_logic_ethernet_RESET_Res
END
BEGIN util_vector_logic
PARAMETER INSTANCE = util_vector_logic_ethernet_AEN
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPERATION = or
PARAMETER C_SIZE = 1
PORT Op1 = net_gnd
PORT Op2 = net_gnd
PORT Res = util_vector_logic_ethernet_AEN_Res
END
BEGIN util_vector_logic
PARAMETER INSTANCE = util_vector_logic_ethernet_ADS
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPERATION = or
PARAMETER C_SIZE = 1
PORT Op1 = net_gnd
PORT Op2 = net_gnd
PORT Res = util_vector_logic_ethernet_ADS_Res
END
MSS
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