It certainly needs to be carefully considered. Different devices have
different properties:
- some must have all buffers (RX and TX) in a defined region of memory
- some must have RX in one region, TX in another
- some can have buffers in one region and use that preferentially for
speed, but can fall back to slower memory if needed
- some can tolerate the 'struct pbuf' header, some can't
- some can scatter gather, some can't
- Some allow entirely variably sized buffers.
- some have fixed size buffers, which may be fixed at the MTU, or may be
smaller; and may be hard-coded for that hardware (e.g. 128 bytes on
AT91SAM7X) or can be any size, but it has to be fixed for all buffers when
the device is initialised.
- some have fixed size buffers and require them to be filled for all but
the final one in the chain
- some have fixed size buffers and don't mind if they are not all filled
- some have associated buffer descriptors which need fiddling with when the
pbuf data becomes available again after having been freed.
- In any of the above, there can be alignment constraints above and beyond
the CPU architectural alignment; most frequently DMA and/or cache line.
And the real annoyance: you could have two different devices with different
(non-overlapping) sets of the above restrictions.