Here is a patch (passes all tests):
diff --git a/ChangeLog b/ChangeLog
index 97263f7..9495b31 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2017-09-04 Marc Nieper-Wisskirchen <address@hidden>
+
+ * include/lightning/jit_x86.h, lib/jit_x86.c: Correct x86_64
+ backend, made %r12 a callee-save register as dictated by the
+ System V AMD64 ABI.
+
2017-06-09 Paulo Andrade <address@hidden>
* include/lightning/jit_private.h, lib/lightning.c: Add a
diff --git a/doc/version.texi b/doc/version.texi
index 7a9127c..99cd7b0 100644
--- a/doc/version.texi
+++ b/doc/version.texi
@@ -1,4 +1,4 @@
address@hidden UPDATED 7 February 2015
address@hidden UPDATED-MONTH February 2015
address@hidden UPDATED 30 August 2017
address@hidden UPDATED-MONTH August 2017
address@hidden EDITION 2.1.0
address@hidden VERSION 2.1.0
diff --git a/include/lightning/jit_x86.h b/include/lightning/jit_x86.h
index c0596b4..0a7af0b 100644
--- a/include/lightning/jit_x86.h
+++ b/include/lightning/jit_x86.h
@@ -117,21 +117,21 @@ typedef enum {
# define jit_sse_reg_p(reg) ((reg) >= _XMM4 && (reg) <= _XMM0)
# else
# define jit_r(i) (_RAX + (i))
-# define jit_r_num() 4
+# define jit_r_num() 3
# define jit_v(i) (_RBX + (i))
-# define jit_v_num() 4
+# define jit_v_num() 5
# define jit_f(index) (_XMM8 + (index))
# define jit_f_num() 8
# define JIT_R0 _RAX
# define JIT_R1 _R10
# define JIT_R2 _R11
-# define JIT_R3 _R12
- _RAX, _R10, _R11, _R12,
+ _RAX, _R10, _R11,
# define JIT_V0 _RBX
-# define JIT_V1 _R13
-# define JIT_V2 _R14
-# define JIT_V3 _R15
- _RBX, _R13, _R14, _R15,
+# define JIT_V1 _R12
+# define JIT_V2 _R13
+# define JIT_V3 _R14
+# define JIT_V4 _R15
+ _RBX, _R12, _R13, _R14, _R15,
_R9, _R8, _RCX, _RDX, _RSI, _RDI,
_RSP, _RBP,
# define JIT_F0 _XMM8
diff --git a/lib/jit_x86.c b/lib/jit_x86.c
index 2e3ba80..649c639 100644
--- a/lib/jit_x86.c
+++ b/lib/jit_x86.c
@@ -185,8 +185,8 @@ jit_register_t _rvs[] = {
{ rc(arg) | rc(gpr) | rc(rg8) | 0, "%rax" },
{ rc(gpr) | rc(rg8) | 10, "%r10" },
{ rc(gpr) | rc(rg8) | 11, "%r11" },
- { rc(gpr) | rc(rg8) | 12, "%r12" },
{ rc(sav) | rc(rg8) | rc(gpr) | 3, "%rbx" },
+ { rc(sav) | rc(rg8) | rc(gpr) | 12, "%r12" },
{ rc(sav) | rc(rg8) | rc(gpr) | 13, "%r13" },
{ rc(sav) | rc(rg8) | rc(gpr) | 14, "%r14" },
{ rc(sav) | rc(rg8) | rc(gpr) | 15, "%r15" },