Hello, I have a general question, where I have my own opinion, but I want to
know what experienced people think.
You are trying to build a large source tree into a number of binary modules. This is one
"configuration/version" of your software, and you want to make multiple
configurations (each with slightly varying options, sets of sources etc). (this is a
common real-life situation I think).
It seems that you have two main choices of how to organize things:
1. Make a shadow source tree of links to the real source tree, one shadow tree
per configuration. Then in each shadow source directory have a small makefile
that just builds the objects in that directory, and it does not need to be told
where the sources are - they are right there in the same directory as links.
Then have a makefile for each module you ultimately build, that links up all
the objects it needs. Here you have a huge number of invocations of make, one
per source directory.
2. Build each module in one directory, objects and all. No links, you have to
tell make where the sources are, you do this with vpath/VPATH , or if you want
to be fast and not search, you implement some kind of advanced automatic
generation of explicit rules for each source file. Here you have a few
invocations of make - one per module.
What I think is 1 is more elegant with all the links and no need to tell make
where sources are, and you can create all the links with one system call on
Linux, but, it is time-costly to create the links, redo them for each
invocation of make as the source tree might have changed, and it takes time to
recursively invoke make so many times.
On contrast, 2 may be ugly, but, especially if you implement explicit rules
without vpath, it ought to be much faster.
What do you think?
Mark
-----Original Message-----
From: address@hidden [mailto:address@hidden On Behalf Of ali hagigat
Sent: Sunday, June 12, 2011 11:27 PM
To: address@hidden; address@hidden
Subject: Re: a question about $(call function
Thanks Mr. Smith for the answer however I have two questions:
1) According to the manual, "If variable is the name of a builtin
function, the builtin function is always invoked ". So why in the
cited example when we have:
var2=$(call $(call var1),pp)
Our variable here is $(call var1) and it is a built in function. Why
it is not called? so:
var2=$(call kk,pp)
var2=pp00
2) if $(call var1)=aba is considered, so:
var2=$(call aba, pp)
var2=pp11
Why var2=aba? why aba function is not called with its $(1)=pp?
Regards
On Mon, Jun 13, 2011 at 1:07 AM, Paul Smith<address@hidden> wrote:
On Sat, 2011-06-11 at 14:49 +0430, ali hagigat wrote:
In the following example with make, 3.81 why var2 is aba?
kk=$(1)00
aba=$(1)11
var1=kk
$(call var1)=aba
var2=$(call $(call var1),pp)
all: ;
$(warning var2=$(var2))
makefile27:7: var2=aba
Because you have "$(call var1)=aba" and $(call var1) expands kk, so this
statement expands to "kk=aba".
--
-------------------------------------------------------------------------------
Paul D. Smith<address@hidden> Find some GNU make tips at:
http://www.gnu.org http://make.mad-scientist.net
"Please remain calm...I may be mad, but I am a professional." --Mad Scientist
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