[Guile-commits] 47/437: refine ludovic's doc patch

[Andy Wingo]

wingo pushed a commit to branch lightning
in repository guile.

commit 36a3ae90588d70aca202dfd9fe5a029560e34709
Author: Paolo Bonzini <address@hidden>
Date:   Thu Nov 23 09:06:07 2006 +0000

    refine ludovic's doc patch
    
    git-archimport-id: address@hidden/lightning--stable--1.2--patch-51
---
 doc/using.texi | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/doc/using.texi b/doc/using.texi
index 173f1e7..332383e 100644
--- a/doc/using.texi
+++ b/doc/using.texi
@@ -100,20 +100,24 @@ preserved across function calls (@code{V0}, @code{V1} and
 @code{R2}).  Six registers are not very much, but this
 restriction was forced by the need to target CISC architectures
 which, like the x86, are poor of registers; anyway, backends can
-specify the actual number of available caller- and callee-save
-registers with the macros @code{JIT_R_NUM} and @code{JIT_V_NUM}.
+specify the actual number of available registers with the macros
address@hidden (for caller-save registers) and @code{JIT_V_NUM}
+(for callee-save registers).
 
-In addition, there is a special @code{RET} register which contains the
-return value of the current function (@emph{not} the return value of
-callees---use the @code{retval} instruction for this).  You should
+In addition, there is a special @code{RET} register which contains
+the return value of the current function (@emph{not} the return value
+of callees---use the @code{retval} instruction for this).  You should
 always remember, however, that writing this register could overwrite
 either a general-purpose register or an incoming parameter, depending
 on the architecture.
 
 There are at least six floating-point registers, named @code{FPR0} to
address@hidden  These are separate from the integer registers on
-all the supported architectures; on Intel architectures, the
-register stack is mapped to a flat register file.
address@hidden  These are caller-save and are separate from the integer
+registers on all the supported architectures; on Intel architectures,
+the register stack is mapped to a flat register file.  As for the
+integer registers, the macro @code{JIT_FPR_NUM} yields the number of
+floating-point registers, and the special @code{FPRET} register contains
+the return value of the current function.
 
 The complete instruction set follows; as you can see, most non-memory
 operations only take integers, long integers (either signed or