[Emacs-diffs] Changes to emacs/lisp/ChangeLog,v [EMACS_22_BASE]

[Dan Nicolaescu]

CVSROOT:        /cvsroot/emacs
Module name:    emacs
Branch:         EMACS_22_BASE
Changes by:     Dan Nicolaescu <dann>   08/02/21 05:15:38

Index: ChangeLog
===================================================================
RCS file: /cvsroot/emacs/emacs/lisp/ChangeLog,v
retrieving revision 1.11049.2.630
retrieving revision 1.11049.2.631
diff -u -b -r1.11049.2.630 -r1.11049.2.631
--- ChangeLog   20 Feb 2008 22:16:05 -0000      1.11049.2.630
+++ ChangeLog   21 Feb 2008 05:15:31 -0000      1.11049.2.631
@@ -1,3 +1,35 @@
+2008-02-21  Michael McNamara  <address@hidden>
+
+       * progmodes/verilog-mode.el (verilog-xemacs-menu): Remove XEmacs
+       conditional.
+       (verilog-font-grouping-keywords-face): Make the begin..end
+       keywords standout more than other verilog keywords.
+        (verilog-type-font-keywords): Move the begin..end out of this list
+       to facilitate making them to (potentially) stand out more.
+       (verilog-backward-token): Fix indent of bare always{_*}?, initial,
+       function & task blocks.
+        (verilog-behavioral-block-beg-re): Fix indent of bare always{_*}?,
+       initial, function & task blocks.
+       (verilog-forward-sexp): Handle the new "disable fork" statement of
+       IEEE-1800 Verilog.
+        (verilog-beg-block-re-ordered): Handle the new "disable fork"
+       statement of IEEE-1800 Verilog.
+        (verilog-calc-1): Handle the new "disable fork" statement of
+       IEEE-1800 Verilog.
+        (verilog-disable-fork-re): Add const to help handle the new
+       "disable fork" statement of IEEE-1800 Verilog.
+       (verilog-declaration-core-re): Add port directions by themselves,
+       with no qualification, as base item of a declaration.
+        (verilog-pretty-declarations): Add new flag to ask it to refrain
+       from printing to the message buffer.
+        (verilog-pretty-expr): Add a QUIET flag to ask it to refrain from
+       printing to the message buffer.  Improve handling of the many
+       types of expression line up.
+        (verilog-just-one-space): Remove printing of an empty message.
+        (verilog-get-lineup-indent): Rework to support the better handling
+       of expression lineup for verilog-pretty-expr.
+        (verilog-auto-wire): Pass the quiet flag to verilog-pretty-expr.
+
 2008-02-20  Alan Mackenzie  <address@hidden>
 
        * progmodes/cc-mode.el (c-extend-region-for-CPP): Bug fix from