[Discuss-gnuradio] [GSoC19]: Weekly report of cycle-accurate Verilog simulation

[Bowen Hu]

Hi all,

Here(https://b0wen-hu.github.io/2019/05/26/GSoC-weekly-report-3/) is my report this week.

The following content is the abstract  of report, please find the full report at the link above.

## Progress this week

I have finished the tutorials from chapter 2 to chapter 7 this week.

​

I have successfully made flicker.v a source block in GNU Radio, and it passed the python QA code. You can find it here.​

​

This source block was implemented by shared library (dynamic-link library) mechanism. This shared library was generated manually, and loaded in the GNU Radio block at runtime. I will explain details later.​

​

As you can know from flicker.v, this verilog module's output would switch between 0 and 31. The QA code of this module is as follow. It stops the code with head block.

## Plan next week

I have created a new repository named gr-verilog on GitHub. This repository would server as the main development repository during the coding period of GSoC19.

​

I will work on the overall structure of the gr-verilog module in the coming week. I will work on the structure branch of gr-verilog.​

​

I will post another report on the overall structure details of gr-verilog module, in the next few days.

## Issue(s)

After three weeks, I will have my final exam. I may need to take some time to review for the exam, but I think I can still catch up. I will do extra work during the weekend.

Best regards,

Bowen