[Discuss-gnuradio] [GSoC19]Few Questions about Cycle-accurate Verilog Design Simulation Integration

[Bowen Hu]

Hi all,

I have read the GSoC ideas page(https://wiki.gnuradio.org/index.php/GSoCIdeas#Hardware_in_the_Loop:_Cycle-accurate_Verilog_Design_Simulation_Integration), and I am interested in the work, Cycle-accurate Verilog Design Simulation Integration. I've been playing around with Verilator these days. And I have some questions about the work.

Verilator can compile Verilog files into C++ class files, which can be included by C++ code and then compiled into cycle-accurate executable model by gcc. The goal is to integrate this function into gnu radio. Would it be appropriate to just call system() function to execute shell command just like doing it manually? Or, is there any better way to realize this procedure?

With the very same question as above for Verilator itself , Would it be appropriate to call shell command to run Verilator just like doing it manually?

If the answers to these questions above are yes, Could I draw the conclusion that the major job I should do in this integration work is to wrap the C++ files generated by Verilator. What I have to do is to convert the data type into something that would work with the C++ class generated by Verilator and make sure they would work as predicted.

Thanks,

Bowen