Re: [Discuss-gnuradio] VHDL code testing with GNURadio?

[CEL]

Hi Murray,

not an expert on the Altera side of things, but generally:

You'll need a simulator as VHDL simply isn't C-calling convention
callable code ;)
So, there's different approaches to that, but as far as I know, noone
has yet written an adapter that somehow (magically?) pipes data into
the Quartus-II-integrated simulator, and back out, from and into GNU
Radio, respectively.
OpenCPI might really be the right way here – haven't played with it,
was just very impressed by their talk at GRCon '17, don't know if they
implement an FPGA simulator interface. But yes, this is FPGA
development – sad reality is that most tools are clunky at best.

But maybe that's also not the way to go. I'd love to see someone write
a bit of glue code for Verilator, so that e.g. RFNoC blocks could be
run directly in software. Would be so much nicer than writing
systemverilog testbenches!

Cheers,
Marcus

On Mon, 2018-08-20 at 16:12 +0100, Murray Thomson wrote:
> Hi,
> 
> I have seen the project openCPI but I'm not sure if this is what I'm looking 
> for. Hoping that someone will point me in the right direction.
> 
> I am writing some VHDL code and I was hoping to use GNURadio to test it. When 
> I'm finished, I will compile and deploy it using Quartus II so I am not 
> looking for full integration, deployment, cross platform... just testing my 
> code as a GNURadio block.
> 
> At the moment I'm using vunit where I have a testbench that reads a file and 
> sends it to my VHDL block and writes the output to another file. 
> 
> Is there any way to create a python or C++ block and in the 'work' function I 
> call whatever magic this vunit is doing? If I could go from a VHDL block to a 
> GNURadio block where I have signals as inputs and outputs I could test it in 
> "real time" which would be awesome. 
> 
> I'm not expecting good performance or lots of features, just inputs and 
> outputs. Is there a project that would help me do this? I have read part of 
> the openCPI documentation that gives me the impression that it could be used 
> but setting that up looks far more complex than the VHDL code that I want to 
> implement... J!
> 
> Cheers,
> Murray
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