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Re: [Discuss-gnuradio] USRP phase to sample index relation in the DDC/DU


From: Marcus Müller
Subject: Re: [Discuss-gnuradio] USRP phase to sample index relation in the DDC/DUC chain
Date: Mon, 3 Jul 2017 21:02:18 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0

Hello Nicolas,

sorry for the delayed reaction!

So, the signal chain looks roughly like this:

RX:

ADC (@Master Clock Rate (MCR) --> Rotator (@MCR) --> decimator --> Host (@user-requested sampling rate)

TX:

Host (@user sampling rate) --> interpolator --> Rotator (@MCR) --> DAC (@MCR)

The two rotators here are the CORDICs you're referring to.

UHD just calculates by how much of the master clock rate you need to rotate per sample – e.g. if you tune digitally by 1 MHz, and your MCR is 200 MHz, then each sample needs to be phase-shifted by $\frac{2\pi}{\frac{\text{MCR}}{f_\text{offset}}}$; ie. you need a multiplicator that takes the input sample, and multiplies it with a complex factor $e^{j\varphi}$; and after each sample, that $\varphi$ needs to be incremented by $\frac{2\pi}{200}$.

Thus, what UHD calculates is exactly that factor of 2π/200 and sends it to the CORDIC unit on the FPGA, which then uses that value as phase increase.

Best regards,

Marcus


On 06/09/2017 11:04 AM, Nicolas GALLAND wrote:
Hello everyone,

I am using a USRP X310 with basic RX and basic TX daughterboards and I would like to know the exact relation between the number I enter as a parameter for the central frequency in the UHD USRP sink/source block (which is a real number) and the actual phase per each sample.

As a matter of facts, if the DDC/DUC chains were using a DDS, the relation would be pretty straightforward (knowing the control word of the DDS and the number of bits of the phase accumulator...). However, as I understand, the FPGA design uses a CORDIC for the DDC/DUC chain, for which the exact correspondence between sample index and phase is not as straight forward to derive. I am sorry if this is textbook material for CORDIC specialists (which I am not...), but I am wondering if someone could point me to the exact formula of phase vs sample index that I could use to very accurately know what is going on in the DDC/DUC chain. The bottom line is that I need to be sure of what is happening at the nrad level for MHz-ish input/output and mod/demod frequency, and the intricacies of the CORDIC behavior is - to my best understanding - playing a major role at this level.

Any help would be greatly appreciated.

Best regards,

    Nicolas


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