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From: | Marcus D. Leech |
Subject: | Re: [Discuss-gnuradio] Phase measurement with Ettus Research N210 |
Date: | Tue, 17 Jun 2014 17:09:10 -0400 |
User-agent: | Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111108 Fedora/3.1.16-1.fc14 Thunderbird/3.1.16 |
On 06/17/2014 04:56 PM, Daniele Nicolodi wrote:
I'll try to see if this makes a difference. The minimum sampling rate I can program is ~193 kHz (it is a strange fraction that I cannot check right now).
Minimum sample rate = 100e6/512 The USRP devices do strictly-integer decimation in the FPGA.
The master clock on the N2xx series is derived from a 10MHz source (on-board 10MHz VCTCXO, or external, or internal GPSDO), feeding an AD9510 PLL clock generator, which in turn controls a 100MHz VFO, implemented with a 100MHz VCTCXO--both clocks are in the 2.5PPM category.Given your explanation I believe that the issue may come from finite accuracy in the generation of the 100 MHz sampling rate: how is the 100 MHz clock generated exactly? If the 100 MHz clock is divided with a DDS to be compared to the 10 MHz clock to derive the error signal for the PLL, the finite precision of the DDS control register may explain the small frequency error (a 32 bit DDS would introduce the right order of magnitude effect, but I haven't check the exact number). Cheers, Daniele
http://files.ettus.com/schematics/n200/n2xx.pdf -- Marcus Leech Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org
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