Sure:
- first the description is correct and not just copied from interp_short.py
- removed the writing to 'atsc_complex.data' as this uses a lot of space and seems to have no meaning outside of debugging
- I use interleave_short_to_complex instead of s2s -> s2f -> f2c chain
- lp_coeffs and duc_coeffs uses input_rate instead of just the number, should make changing it easier
- lp_coeffs no longer arbitrarily adds 3 gain
- duc now shifts the frequency in the correct direction
- the root raised cosine filter taps no longer need to be heterodyned into place as I just use it at baseband
- the root raised cosine filer gets used now ( for some reason it was not in the chain before and this was severely causing ISI )
- lower_edge and upper_edge seemed arbitrary and were not in the right spot anyway
After this stuff and the reorganization a simple diff would not have saved much,
also i'm working on 'atsc_tx.py',so 'all_atsc.py' would be confusing, hence the name change.
Also the other scripts seem unnecessary with the new thread-per-block sceduler, the also seem to cause
a lot of beginners confusion. So I felt they needed to go.
I have also built a ( semi ) working complex fpll for gr-atsc, this removes the need for up-converting and the filtering
after the current fpll, my next atsc_rx will need the new script style. After I finish updating the bit timing loop
we will be almost real time I believe!
P.S. I could still just do the diff to the old all_atsc.py and rename if you want.
Thank you
Andrew