What do you mean by different? Do they behave different? Or you used a program to compare the binary data comparison between the 2 and this is what you are saying here?
Xilinx P&R tool as well as it's resource optimizer and mapper use special algorithm that creates a random path of data for
each run, unless you hard code your blocks and force the MAP and P&R not to touch the blocks, the result of the 2 identical compilation will be different.
If there are any clocks in the whole design that is not included in the UCF file, then the MAP will try to find the best placement for it which in almost 99% of the cases when you start a new compile, is different than the one created earlier.
Xilinx supports partial re-configuration on some it's devices as it is described here:
http://www.xilinx.com/tools/partial-reconfiguration.htm and that can help those who want to make sure that the differences between different version of the code/compiles are minimum, but this is not supported only by the Virtex family of devices and not the Spartan series.
Just my 2c!
BR,
Farhad