Hi,
I've downloaded the source of the Spartan 3 design of USRP2 from the
repository git://git.ettus.com/ettus/fpga.git, and i compiled it with
the makefile in usrp2/top/u2_rev3.
I have Xilinx ISE 12.1 system edition in linux (ubuntu 10.04).
The whole process goes well, and the bin file is generated without
errors. (I tested it also on the windows versione of ISE by the way,
same results).
The fact is that when i put it in the SD for some testing, the USRP2
is not recognized anymore by the host computer. The D led does not
turn on.
This is a mess because i need to modify the design, but if even the
base design is not working, i can't do anything. I have my new design
which is working (from the simulations), so this is the only problem
that i have to finish my work.
Looking at the bin file that have been generated, i notice that the
dimension is 862580 byte, against 862584 byte of the
u2_rev3-20100603.bin that can be downloaded from the gnuradio site
(and that is working if i use it on the SD card).
I don't know what to do, i did not change anything to test the base
design, i just downloaded it and used the make command.
Opening the .xise project, i can see that there is a failing timing
constant (i paste here the details). Where is the problem?
Which is the ise version that are you using? (maybe the 12.2?)
Do i need to change the firmware (there is an old one on, which is working)
Thank you in advance.
================================================================================
Timing constraint: TS_clk_div = PERIOD TIMEGRP "clk_div"
TS_clk_fpga_p * 2 HIGH 50%;
1950815 paths analyzed, 12650 endpoints analyzed, 1 failing endpoint
1 timing error detected. (1 setup error, 0 hold errors, 0 component
switching limit errors)
Minimum period is 20.660ns.
--------------------------------------------------------------------------------
Paths for end point u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (R18.O1),
10301 paths
--------------------------------------------------------------------------------
Slack (setup path): -0.660ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/buffer_pool/gen_buffer[6].dpram.A (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.660ns (Levels of Logic = 14)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/buffer_pool/gen_buffer[6].dpram.A to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y17.DOA1 Tbcko 2.082
u2_core/buffer_pool/gen_buffer[6].dpram
u2_core/buffer_pool/gen_buffer[6].dpram.A
SLICE_X118Y104.F4 net (fanout=1) 1.788
u2_core/buffer_pool/buf_doa<6><1>
SLICE_X118Y104.F5 Tif5 0.693 u2_core/s1_dat_i<1>
u2_core/buffer_pool/Mmux_wb_dat_o_411
u2_core/buffer_pool/Mmux_wb_dat_o_3_f5_10
SLICE_X118Y104.FXINA net (fanout=1) 0.000
u2_core/buffer_pool/Mmux_wb_dat_o_3_f511
SLICE_X118Y104.Y Tif6y 0.298 u2_core/s1_dat_i<1>
u2_core/buffer_pool/Mmux_wb_dat_o_2_f6_10
SLICE_X107Y102.F1 net (fanout=1) 0.888 u2_core/s1_dat_i<1>
SLICE_X107Y102.X Tilo 0.479
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
SLICE_X107Y101.F3 net (fanout=1) 0.319
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
SLICE_X107Y101.X Tilo 0.479
u2_core/atr_controller/atr_ram<13><6>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>90_SW0
SLICE_X94Y84.F2 net (fanout=1) 1.270 N2681
SLICE_X94Y84.X Tilo 0.529
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.F1 net (fanout=2) 1.177
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.X Tilo 0.479
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>174
SLICE_X107Y75.F1 net (fanout=6) 0.835
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
SLICE_X107Y75.X Tif5x 0.793
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_311
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_10
SLICE_X104Y72.G2 net (fanout=83) 1.119
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
SLICE_X104Y72.COUT Topcyg 0.954
u2_core/aeMB/aeMB_edk32/xecu/wADD<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_lut<1>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.660ns (9.924ns
logic, 10.736ns route)
(48.0% logic,
52.0% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.480ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/buffer_pool/gen_buffer[6].dpram.A (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.480ns (Levels of Logic = 14)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/buffer_pool/gen_buffer[6].dpram.A to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y17.DOA1 Tbcko 2.082
u2_core/buffer_pool/gen_buffer[6].dpram
u2_core/buffer_pool/gen_buffer[6].dpram.A
SLICE_X118Y104.F4 net (fanout=1) 1.788
u2_core/buffer_pool/buf_doa<6><1>
SLICE_X118Y104.F5 Tif5 0.693 u2_core/s1_dat_i<1>
u2_core/buffer_pool/Mmux_wb_dat_o_411
u2_core/buffer_pool/Mmux_wb_dat_o_3_f5_10
SLICE_X118Y104.FXINA net (fanout=1) 0.000
u2_core/buffer_pool/Mmux_wb_dat_o_3_f511
SLICE_X118Y104.Y Tif6y 0.298 u2_core/s1_dat_i<1>
u2_core/buffer_pool/Mmux_wb_dat_o_2_f6_10
SLICE_X107Y102.F1 net (fanout=1) 0.888 u2_core/s1_dat_i<1>
SLICE_X107Y102.X Tilo 0.479
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
SLICE_X107Y101.F3 net (fanout=1) 0.319
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
SLICE_X107Y101.X Tilo 0.479
u2_core/atr_controller/atr_ram<13><6>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>90_SW0
SLICE_X94Y84.F2 net (fanout=1) 1.270 N2681
SLICE_X94Y84.X Tilo 0.529
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.F1 net (fanout=2) 1.177
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.X Tilo 0.479
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>174
SLICE_X107Y75.F1 net (fanout=6) 0.835
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
SLICE_X107Y75.X Tif5x 0.793
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_311
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_10
SLICE_X104Y72.G2 net (fanout=83) 1.119
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
SLICE_X104Y72.COUT Topcyg 0.774
u2_core/aeMB/aeMB_edk32/xecu/wADD<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.480ns (9.744ns
logic, 10.736ns route)
(47.6% logic,
52.4% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.460ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/buffer_pool/gen_buffer[6].dpram.A (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.460ns (Levels of Logic = 14)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/buffer_pool/gen_buffer[6].dpram.A to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y17.DOA16 Tbcko 2.082
u2_core/buffer_pool/gen_buffer[6].dpram
u2_core/buffer_pool/gen_buffer[6].dpram.A
SLICE_X117Y102.F4 net (fanout=1) 2.073
u2_core/buffer_pool/buf_doa<6><16>
SLICE_X117Y102.F5 Tif5 0.643 u2_core/s1_dat_i<16>
u2_core/buffer_pool/Mmux_wb_dat_o_47
u2_core/buffer_pool/Mmux_wb_dat_o_3_f5_6
SLICE_X117Y102.FXINA net (fanout=1) 0.000
u2_core/buffer_pool/Mmux_wb_dat_o_3_f57
SLICE_X117Y102.Y Tif6y 0.298 u2_core/s1_dat_i<16>
u2_core/buffer_pool/Mmux_wb_dat_o_2_f6_6
SLICE_X104Y89.F4 net (fanout=1) 1.117 u2_core/s1_dat_i<16>
SLICE_X104Y89.X Tilo 0.529
u2_core/wb_1master/i_dat_s<16>28
u2_core/wb_1master/i_dat_s<16>28
SLICE_X102Y90.F4 net (fanout=1) 0.313
u2_core/wb_1master/i_dat_s<16>28
SLICE_X102Y90.X Tilo 0.529 u2_core/m0_dat_o<16>
u2_core/wb_1master/i_dat_s<16>109
SLICE_X107Y88.F4 net (fanout=5) 1.655 u2_core/m0_dat_o<16>
SLICE_X107Y88.X Tilo 0.479
u2_core/pic/irq_event<25>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<0>22
SLICE_X106Y86.G4 net (fanout=2) 0.359
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<0>22
SLICE_X106Y86.Y Tilo 0.529
u2_core/time_sync/tick_time<11>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<0>174
SLICE_X107Y78.G1 net (fanout=6) 1.034
u2_core/aeMB/aeMB_edk32/rDWBDI<0>
SLICE_X107Y78.Y Tilo 0.479
u2_core/atr_controller/atr_ram<7><1>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPA2
SLICE_X104Y72.F2 net (fanout=11) 0.919
u2_core/aeMB/aeMB_edk32/xecu/rOPA<0>1
SLICE_X104Y72.COUT Topcyf 0.944
u2_core/aeMB/aeMB_edk32/xecu/wADD<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_lut<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.460ns (9.650ns
logic, 10.810ns route)
(47.2% logic,
52.8% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.356ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/buffer_pool/gen_buffer[6].dpram.A (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.356ns (Levels of Logic = 13)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/buffer_pool/gen_buffer[6].dpram.A to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y17.DOA18 Tbcko 2.082
u2_core/buffer_pool/gen_buffer[6].dpram
u2_core/buffer_pool/gen_buffer[6].dpram.A
SLICE_X114Y104.F3 net (fanout=1) 2.159
u2_core/buffer_pool/buf_doa<6><18>
SLICE_X114Y104.F5 Tif5 0.693 u2_core/s1_dat_i<18>
u2_core/buffer_pool/Mmux_wb_dat_o_49
u2_core/buffer_pool/Mmux_wb_dat_o_3_f5_8
SLICE_X114Y104.FXINA net (fanout=1) 0.000
u2_core/buffer_pool/Mmux_wb_dat_o_3_f59
SLICE_X114Y104.Y Tif6y 0.298 u2_core/s1_dat_i<18>
u2_core/buffer_pool/Mmux_wb_dat_o_2_f6_8
SLICE_X100Y99.F3 net (fanout=1) 1.014 u2_core/s1_dat_i<18>
SLICE_X100Y99.X Tilo 0.529
u2_core/timer/time_wb<22>
u2_core/wb_1master/i_dat_s<18>28
SLICE_X99Y97.F4 net (fanout=1) 0.313
u2_core/wb_1master/i_dat_s<18>28
SLICE_X99Y97.X Tilo 0.479 u2_core/nsgpio/ctrl<26>
u2_core/wb_1master/i_dat_s<18>109
SLICE_X104Y90.G2 net (fanout=5) 1.734 u2_core/m0_dat_o<18>
SLICE_X104Y90.Y Tilo 0.529
u2_core/timer/time_wb<20>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<2>22
SLICE_X104Y90.F4 net (fanout=2) 0.017
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<2>22
SLICE_X104Y90.X Tilo 0.529
u2_core/timer/time_wb<20>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<2>174
SLICE_X105Y76.F4 net (fanout=6) 0.738
u2_core/aeMB/aeMB_edk32/rDWBDI<2>
SLICE_X105Y76.X Tif5x 0.793
u2_core/aeMB/aeMB_edk32/xecu/rOPB<2>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_322
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_21
SLICE_X104Y73.F1 net (fanout=127) 1.131
u2_core/aeMB/aeMB_edk32/xecu/rOPB<2>
SLICE_X104Y73.COUT Topcyf 0.944
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_lut<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.356ns (9.910ns
logic, 10.446ns route)
(48.7% logic,
51.3% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.295ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/buffer_pool/gen_buffer[2].dpram.A (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.295ns (Levels of Logic = 14)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/buffer_pool/gen_buffer[2].dpram.A to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y16.DOA1 Tbcko 2.082
u2_core/buffer_pool/gen_buffer[2].dpram
u2_core/buffer_pool/gen_buffer[2].dpram.A
SLICE_X118Y105.F4 net (fanout=1) 1.423
u2_core/buffer_pool/buf_doa<2><1>
SLICE_X118Y105.F5 Tif5 0.693
u2_core/buffer_pool/Mmux_wb_dat_o_4_f511
u2_core/buffer_pool/Mmux_wb_dat_o_523
u2_core/buffer_pool/Mmux_wb_dat_o_4_f5_10
SLICE_X118Y104.FXINB net (fanout=1) 0.000
u2_core/buffer_pool/Mmux_wb_dat_o_4_f511
SLICE_X118Y104.Y Tif6y 0.298 u2_core/s1_dat_i<1>
u2_core/buffer_pool/Mmux_wb_dat_o_2_f6_10
SLICE_X107Y102.F1 net (fanout=1) 0.888 u2_core/s1_dat_i<1>
SLICE_X107Y102.X Tilo 0.479
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
SLICE_X107Y101.F3 net (fanout=1) 0.319
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
SLICE_X107Y101.X Tilo 0.479
u2_core/atr_controller/atr_ram<13><6>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>90_SW0
SLICE_X94Y84.F2 net (fanout=1) 1.270 N2681
SLICE_X94Y84.X Tilo 0.529
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.F1 net (fanout=2) 1.177
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.X Tilo 0.479
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>174
SLICE_X107Y75.F1 net (fanout=6) 0.835
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
SLICE_X107Y75.X Tif5x 0.793
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_311
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_10
SLICE_X104Y72.G2 net (fanout=83) 1.119
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
SLICE_X104Y72.COUT Topcyg 0.954
u2_core/aeMB/aeMB_edk32/xecu/wADD<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_lut<1>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.295ns (9.924ns
logic, 10.371ns route)
(48.9% logic,
51.1% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.295ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/buffer_pool/gen_buffer[0].dpram.A (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.295ns (Levels of Logic = 14)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/buffer_pool/gen_buffer[0].dpram.A to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y10.DOA1 Tbcko 2.082
u2_core/buffer_pool/gen_buffer[0].dpram
u2_core/buffer_pool/gen_buffer[0].dpram.A
SLICE_X118Y105.G3 net (fanout=1) 1.423
u2_core/buffer_pool/buf_doa<0><1>
SLICE_X118Y105.F5 Tif5 0.693
u2_core/buffer_pool/Mmux_wb_dat_o_4_f511
u2_core/buffer_pool/Mmux_wb_dat_o_611
u2_core/buffer_pool/Mmux_wb_dat_o_4_f5_10
SLICE_X118Y104.FXINB net (fanout=1) 0.000
u2_core/buffer_pool/Mmux_wb_dat_o_4_f511
SLICE_X118Y104.Y Tif6y 0.298 u2_core/s1_dat_i<1>
u2_core/buffer_pool/Mmux_wb_dat_o_2_f6_10
SLICE_X107Y102.F1 net (fanout=1) 0.888 u2_core/s1_dat_i<1>
SLICE_X107Y102.X Tilo 0.479
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
SLICE_X107Y101.F3 net (fanout=1) 0.319
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>75
SLICE_X107Y101.X Tilo 0.479
u2_core/atr_controller/atr_ram<13><6>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>90_SW0
SLICE_X94Y84.F2 net (fanout=1) 1.270 N2681
SLICE_X94Y84.X Tilo 0.529
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.F1 net (fanout=2) 1.177
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.X Tilo 0.479
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>174
SLICE_X107Y75.F1 net (fanout=6) 0.835
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
SLICE_X107Y75.X Tif5x 0.793
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_311
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_10
SLICE_X104Y72.G2 net (fanout=83) 1.119
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
SLICE_X104Y72.COUT Topcyg 0.954
u2_core/aeMB/aeMB_edk32/xecu/wADD<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_lut<1>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.295ns (9.924ns
logic, 10.371ns route)
(48.9% logic,
51.1% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.283ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/buffer_pool/gen_buffer[6].dpram.A (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.283ns (Levels of Logic = 14)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/buffer_pool/gen_buffer[6].dpram.A to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y17.DOA16 Tbcko 2.082
u2_core/buffer_pool/gen_buffer[6].dpram
u2_core/buffer_pool/gen_buffer[6].dpram.A
SLICE_X117Y102.F4 net (fanout=1) 2.073
u2_core/buffer_pool/buf_doa<6><16>
SLICE_X117Y102.F5 Tif5 0.643 u2_core/s1_dat_i<16>
u2_core/buffer_pool/Mmux_wb_dat_o_47
u2_core/buffer_pool/Mmux_wb_dat_o_3_f5_6
SLICE_X117Y102.FXINA net (fanout=1) 0.000
u2_core/buffer_pool/Mmux_wb_dat_o_3_f57
SLICE_X117Y102.Y Tif6y 0.298 u2_core/s1_dat_i<16>
u2_core/buffer_pool/Mmux_wb_dat_o_2_f6_6
SLICE_X104Y89.F4 net (fanout=1) 1.117 u2_core/s1_dat_i<16>
SLICE_X104Y89.X Tilo 0.529
u2_core/wb_1master/i_dat_s<16>28
u2_core/wb_1master/i_dat_s<16>28
SLICE_X102Y90.F4 net (fanout=1) 0.313
u2_core/wb_1master/i_dat_s<16>28
SLICE_X102Y90.X Tilo 0.529 u2_core/m0_dat_o<16>
u2_core/wb_1master/i_dat_s<16>109
SLICE_X107Y88.F4 net (fanout=5) 1.655 u2_core/m0_dat_o<16>
SLICE_X107Y88.X Tilo 0.479
u2_core/pic/irq_event<25>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<0>22
SLICE_X106Y86.G4 net (fanout=2) 0.359
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<0>22
SLICE_X106Y86.Y Tilo 0.529
u2_core/time_sync/tick_time<11>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<0>174
SLICE_X107Y72.F1 net (fanout=6) 0.915
u2_core/aeMB/aeMB_edk32/rDWBDI<0>
SLICE_X107Y72.X Tif5x 0.793
u2_core/aeMB/aeMB_edk32/xecu/rOPB<0>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_3
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5
SLICE_X104Y72.F1 net (fanout=82) 0.547
u2_core/aeMB/aeMB_edk32/xecu/rOPB<0>
SLICE_X104Y72.COUT Topcyf 0.944
u2_core/aeMB/aeMB_edk32/xecu/wADD<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_lut<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.283ns (9.964ns
logic, 10.319ns route)
(49.1% logic,
50.9% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.252ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/sys_ram/sys_ram/Mram_ram01.B (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.252ns (Levels of Logic = 11)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/sys_ram/sys_ram/Mram_ram01.B to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X0Y4.DOB1 Tbcko 2.082
u2_core/sys_ram/sys_ram/Mram_ram01
u2_core/sys_ram/sys_ram/Mram_ram01.B
SLICE_X94Y85.G4 net (fanout=1) 5.263 u2_core/s0_dat_i<1>
SLICE_X94Y85.Y Tilo 0.529
u2_core/atr_controller/atr_ram<12><21>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>80
SLICE_X94Y84.F3 net (fanout=1) 0.014
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>80
SLICE_X94Y84.X Tilo 0.529
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.F1 net (fanout=2) 1.177
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>162
SLICE_X107Y80.X Tilo 0.479
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<1>174
SLICE_X107Y75.F1 net (fanout=6) 0.835
u2_core/aeMB/aeMB_edk32/rDWBDI<1>
SLICE_X107Y75.X Tif5x 0.793
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_311
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_10
SLICE_X104Y72.G2 net (fanout=83) 1.119
u2_core/aeMB/aeMB_edk32/xecu/rOPB<1>
SLICE_X104Y72.COUT Topcyg 0.954
u2_core/aeMB/aeMB_edk32/xecu/wADD<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_lut<1>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.252ns (8.504ns
logic, 11.748ns route)
(42.0% logic,
58.0% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.224ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/buffer_pool/gen_buffer[0].dpram.A (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.224ns (Levels of Logic = 14)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/buffer_pool/gen_buffer[0].dpram.A to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y10.DOA16 Tbcko 2.082
u2_core/buffer_pool/gen_buffer[0].dpram
u2_core/buffer_pool/gen_buffer[0].dpram.A
SLICE_X117Y103.G3 net (fanout=1) 1.837
u2_core/buffer_pool/buf_doa<0><16>
SLICE_X117Y103.F5 Tif5 0.643
u2_core/buffer_pool/Mmux_wb_dat_o_4_f57
u2_core/buffer_pool/Mmux_wb_dat_o_67
u2_core/buffer_pool/Mmux_wb_dat_o_4_f5_6
SLICE_X117Y102.FXINB net (fanout=1) 0.000
u2_core/buffer_pool/Mmux_wb_dat_o_4_f57
SLICE_X117Y102.Y Tif6y 0.298 u2_core/s1_dat_i<16>
u2_core/buffer_pool/Mmux_wb_dat_o_2_f6_6
SLICE_X104Y89.F4 net (fanout=1) 1.117 u2_core/s1_dat_i<16>
SLICE_X104Y89.X Tilo 0.529
u2_core/wb_1master/i_dat_s<16>28
u2_core/wb_1master/i_dat_s<16>28
SLICE_X102Y90.F4 net (fanout=1) 0.313
u2_core/wb_1master/i_dat_s<16>28
SLICE_X102Y90.X Tilo 0.529 u2_core/m0_dat_o<16>
u2_core/wb_1master/i_dat_s<16>109
SLICE_X107Y88.F4 net (fanout=5) 1.655 u2_core/m0_dat_o<16>
SLICE_X107Y88.X Tilo 0.479
u2_core/pic/irq_event<25>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<0>22
SLICE_X106Y86.G4 net (fanout=2) 0.359
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<0>22
SLICE_X106Y86.Y Tilo 0.529
u2_core/time_sync/tick_time<11>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<0>174
SLICE_X107Y78.G1 net (fanout=6) 1.034
u2_core/aeMB/aeMB_edk32/rDWBDI<0>
SLICE_X107Y78.Y Tilo 0.479
u2_core/atr_controller/atr_ram<7><1>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPA2
SLICE_X104Y72.F2 net (fanout=11) 0.919
u2_core/aeMB/aeMB_edk32/xecu/rOPA<0>1
SLICE_X104Y72.COUT Topcyf 0.944
u2_core/aeMB/aeMB_edk32/xecu/wADD<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_lut<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<0>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<1>
SLICE_X104Y73.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.224ns (9.650ns
logic, 10.574ns route)
(47.7% logic,
52.3% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.203ns (requirement - (data path - clock
path skew + uncertainty))
Source: u2_core/buffer_pool/gen_buffer[6].dpram.A (RAM)
Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF)
Requirement: 20.000ns
Data Path Delay: 20.203ns (Levels of Logic = 13)
Clock Path Skew: 0.000ns
Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns
Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: u2_core/buffer_pool/gen_buffer[6].dpram.A to
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y17.DOA18 Tbcko 2.082
u2_core/buffer_pool/gen_buffer[6].dpram
u2_core/buffer_pool/gen_buffer[6].dpram.A
SLICE_X114Y104.F3 net (fanout=1) 2.159
u2_core/buffer_pool/buf_doa<6><18>
SLICE_X114Y104.F5 Tif5 0.693 u2_core/s1_dat_i<18>
u2_core/buffer_pool/Mmux_wb_dat_o_49
u2_core/buffer_pool/Mmux_wb_dat_o_3_f5_8
SLICE_X114Y104.FXINA net (fanout=1) 0.000
u2_core/buffer_pool/Mmux_wb_dat_o_3_f59
SLICE_X114Y104.Y Tif6y 0.298 u2_core/s1_dat_i<18>
u2_core/buffer_pool/Mmux_wb_dat_o_2_f6_8
SLICE_X100Y99.F3 net (fanout=1) 1.014 u2_core/s1_dat_i<18>
SLICE_X100Y99.X Tilo 0.529
u2_core/timer/time_wb<22>
u2_core/wb_1master/i_dat_s<18>28
SLICE_X99Y97.F4 net (fanout=1) 0.313
u2_core/wb_1master/i_dat_s<18>28
SLICE_X99Y97.X Tilo 0.479 u2_core/nsgpio/ctrl<26>
u2_core/wb_1master/i_dat_s<18>109
SLICE_X104Y90.G2 net (fanout=5) 1.734 u2_core/m0_dat_o<18>
SLICE_X104Y90.Y Tilo 0.529
u2_core/timer/time_wb<20>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<2>22
SLICE_X104Y90.F4 net (fanout=2) 0.017
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<2>22
SLICE_X104Y90.X Tilo 0.529
u2_core/timer/time_wb<20>
u2_core/aeMB/aeMB_edk32/regf/rDWBDI<2>174
SLICE_X105Y76.F4 net (fanout=6) 0.738
u2_core/aeMB/aeMB_edk32/rDWBDI<2>
SLICE_X105Y76.X Tif5x 0.793
u2_core/aeMB/aeMB_edk32/xecu/rOPB<2>
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_322
u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_21
SLICE_X104Y73.F1 net (fanout=127) 1.131
u2_core/aeMB/aeMB_edk32/xecu/rOPB<2>
SLICE_X104Y73.COUT Topcyf 0.791
u2_core/aeMB/aeMB_edk32/xecu/wADD<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<2>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<3>
SLICE_X104Y74.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<4>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<5>
SLICE_X104Y75.COUT Tbyp 0.104
u2_core/aeMB/aeMB_edk32/xecu/wADD<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<6>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.CIN net (fanout=1) 0.000
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<7>
SLICE_X104Y76.Y Tciny 0.803
u2_core/aeMB/aeMB_edk32/xecu/wADD<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_cy<8>
u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_104_addsub0000_xor<9>
SLICE_X110Y72.G4 net (fanout=1) 0.782
u2_core/aeMB/aeMB_edk32/xecu/wADD<9>
SLICE_X110Y72.X Tif5x 0.843 N3667
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0
SLICE_X116Y61.G3 net (fanout=1) 1.030 N3667
SLICE_X116Y61.Y Tilo 0.529
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177
R18.O1 net (fanout=1) 1.528
u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>
R18.OTCLK1 Tioock 0.651 RAM_A<8>
u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9
-------------------------------------------------
---------------------------
Total 20.203ns (9.757ns
logic, 10.446ns route)
(48.3% logic,
51.7% route)
--------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_clk_fpga_p
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period
| Timing Errors | Paths Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct |
Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_fpga_p | 10.000ns| 5.987ns|
10.330ns| 0| 1| 6| 2423305|
| TS_dcm_out | 10.000ns| 9.941ns|
N/A| 0| 0| 472490| 0|
| TS_clk_div | 20.000ns| 20.660ns|
N/A| 1| 0| 1950815| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock GMII_RX_CLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
GMII_RX_CLK | 7.956| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk_fpga_n
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_fpga_n | 20.660| 3.001| 4.575| |
clk_fpga_p | 20.660| 3.001| 4.575| |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk_fpga_p
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_fpga_n | 20.660| 3.001| 4.575| |
clk_fpga_p | 20.660| 3.001| 4.575| |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk_to_mac
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_to_mac | 7.825| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock cpld_clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cpld_clk | 6.831| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock ser_rx_clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ser_rx_clk | 9.752| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 1 Score: 660 (Setup/Max: 660, Hold: 0)
Constraints cover 2457758 paths, 0 nets, and 93134 connections
Design statistics:
Minimum period: 20.660ns (Maximum frequency: 48.403MHz)
Maximum path delay from/to any node: 9.737ns
Analysis completed Wed Sep 1 10:55:58 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 319 MB