-------------------------------------------------------------------------------- Release 12.1 Trace (lin) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. /export/Xilinx/12.1/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -e 10 -s 5 -n 3 -fastpaths -xml u2_rev3.twx u2_rev3.ncd -o u2_rev3.twr u2_rev3.pcf Design file: u2_rev3.ncd Physical constraint file: u2_rev3.pcf Device,package,speed: xc3s2000,fg456,-5 (PRODUCTION 1.39 2010-04-09) Report level: error report, limited to 10 items per endpoint, 3 endpoints per constraint Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error. ================================================================================ Timing constraint: TS_clk_to_mac = PERIOD TIMEGRP "clk_to_mac" 8 ns HIGH 50%; 6393 paths analyzed, 1272 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 7.909ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clk_fpga_p = PERIOD TIMEGRP "clk_fpga_p" 10 ns HIGH 50%; 6 paths analyzed, 6 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 5.987ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_cpld_clk = PERIOD TIMEGRP "cpld_clk" 40 ns HIGH 50%; 519 paths analyzed, 104 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 7.390ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 8 ns HIGH 50%; 8201 paths analyzed, 1191 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 7.837ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_ser_rx_clk = PERIOD TIMEGRP "ser_rx_clk" 10 ns HIGH 50%; 44 paths analyzed, 14 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 6.747ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clk_div_to_dsp_clk = MAXDELAY FROM TIMEGRP "clk_div" TO TIMEGRP "dcm_out" 10 ns; 19534 paths analyzed, 7884 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 9.867ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_dcm_out = PERIOD TIMEGRP "dcm_out" TS_clk_fpga_p HIGH 50%; 467329 paths analyzed, 38958 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 9.974ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clk_div = PERIOD TIMEGRP "clk_div" TS_clk_fpga_p * 2 HIGH 50%; 1822572 paths analyzed, 10271 endpoints analyzed, 1 failing endpoint 1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors) Minimum period is 20.699ns. -------------------------------------------------------------------------------- Paths for end point u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (R18.O1), 9984 paths -------------------------------------------------------------------------------- Slack (setup path): -0.699ns (requirement - (data path - clock path skew + uncertainty)) Source: u2_core/sys_ram/sys_ram/Mram_ram33.B (RAM) Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF) Requirement: 20.000ns Data Path Delay: 20.699ns (Levels of Logic = 9) Clock Path Skew: 0.000ns Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: u2_core/sys_ram/sys_ram/Mram_ram33.B to u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB16_X0Y17.DOB1 Tbcko 2.082 u2_core/sys_ram/sys_ram/Mram_ram33 u2_core/sys_ram/sys_ram/Mram_ram33.B SLICE_X84Y67.G3 net (fanout=1) 5.634 u2_core/s0_dat_i<29> SLICE_X84Y67.Y Tilo 0.529 u2_core/shared_spi/wb_dat_o<18> u2_core/wb_1master/i_dat_s<29>4 SLICE_X84Y66.G3 net (fanout=1) 0.020 u2_core/wb_1master/i_dat_s<29>4 SLICE_X84Y66.Y Tilo 0.529 u2_core/time_sync/tick_time<30> u2_core/wb_1master/i_dat_s<29>109 SLICE_X86Y62.F3 net (fanout=7) 1.644 u2_core/m0_dat_o<29> SLICE_X86Y62.X Tilo 0.529 u2_core/timer/time_wb<5> u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>112 SLICE_X87Y48.F4 net (fanout=6) 0.717 u2_core/aeMB/aeMB_edk32/rDWBDI<5> SLICE_X87Y48.X Tif5x 0.793 u2_core/pic/pol<21> u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_327 u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_26 SLICE_X82Y48.G2 net (fanout=3) 1.098 u2_core/aeMB/aeMB_edk32/xecu/rOPB<5> SLICE_X82Y48.COUT Topcyg 0.954 u2_core/pic/irq_event<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_lut<5> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.COUT Tbyp 0.104 u2_core/pic/pol<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<6> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.Y Tciny 0.803 u2_core/aeMB/aeMB_edk32/xecu/wADD<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_xor<9> SLICE_X86Y48.G3 net (fanout=1) 0.613 u2_core/aeMB/aeMB_edk32/xecu/wADD<9> SLICE_X86Y48.X Tif5x 0.843 u2_core/pic/pol<17> u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0 SLICE_X104Y49.G3 net (fanout=1) 1.072 N3666 SLICE_X104Y49.Y Tilo 0.529 u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177 R18.O1 net (fanout=1) 1.555 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9> R18.OTCLK1 Tioock 0.651 RAM_A<8> u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 ------------------------------------------------- --------------------------- Total 20.699ns (8.346ns logic, 12.353ns route) (40.3% logic, 59.7% route) -------------------------------------------------------------------------------- Slack (setup path): -0.519ns (requirement - (data path - clock path skew + uncertainty)) Source: u2_core/sys_ram/sys_ram/Mram_ram33.B (RAM) Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF) Requirement: 20.000ns Data Path Delay: 20.519ns (Levels of Logic = 9) Clock Path Skew: 0.000ns Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: u2_core/sys_ram/sys_ram/Mram_ram33.B to u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB16_X0Y17.DOB1 Tbcko 2.082 u2_core/sys_ram/sys_ram/Mram_ram33 u2_core/sys_ram/sys_ram/Mram_ram33.B SLICE_X84Y67.G3 net (fanout=1) 5.634 u2_core/s0_dat_i<29> SLICE_X84Y67.Y Tilo 0.529 u2_core/shared_spi/wb_dat_o<18> u2_core/wb_1master/i_dat_s<29>4 SLICE_X84Y66.G3 net (fanout=1) 0.020 u2_core/wb_1master/i_dat_s<29>4 SLICE_X84Y66.Y Tilo 0.529 u2_core/time_sync/tick_time<30> u2_core/wb_1master/i_dat_s<29>109 SLICE_X86Y62.F3 net (fanout=7) 1.644 u2_core/m0_dat_o<29> SLICE_X86Y62.X Tilo 0.529 u2_core/timer/time_wb<5> u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>112 SLICE_X87Y48.F4 net (fanout=6) 0.717 u2_core/aeMB/aeMB_edk32/rDWBDI<5> SLICE_X87Y48.X Tif5x 0.793 u2_core/pic/pol<21> u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_327 u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_26 SLICE_X82Y48.G2 net (fanout=3) 1.098 u2_core/aeMB/aeMB_edk32/xecu/rOPB<5> SLICE_X82Y48.COUT Topcyg 0.774 u2_core/pic/irq_event<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.COUT Tbyp 0.104 u2_core/pic/pol<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<6> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.Y Tciny 0.803 u2_core/aeMB/aeMB_edk32/xecu/wADD<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_xor<9> SLICE_X86Y48.G3 net (fanout=1) 0.613 u2_core/aeMB/aeMB_edk32/xecu/wADD<9> SLICE_X86Y48.X Tif5x 0.843 u2_core/pic/pol<17> u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0 SLICE_X104Y49.G3 net (fanout=1) 1.072 N3666 SLICE_X104Y49.Y Tilo 0.529 u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177 R18.O1 net (fanout=1) 1.555 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9> R18.OTCLK1 Tioock 0.651 RAM_A<8> u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 ------------------------------------------------- --------------------------- Total 20.519ns (8.166ns logic, 12.353ns route) (39.8% logic, 60.2% route) -------------------------------------------------------------------------------- Slack (setup path): -0.466ns (requirement - (data path - clock path skew + uncertainty)) Source: u2_core/sys_ram/sys_ram/Mram_ram33.B (RAM) Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF) Requirement: 20.000ns Data Path Delay: 20.466ns (Levels of Logic = 9) Clock Path Skew: 0.000ns Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: u2_core/sys_ram/sys_ram/Mram_ram33.B to u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB16_X0Y17.DOB1 Tbcko 2.082 u2_core/sys_ram/sys_ram/Mram_ram33 u2_core/sys_ram/sys_ram/Mram_ram33.B SLICE_X84Y67.G3 net (fanout=1) 5.634 u2_core/s0_dat_i<29> SLICE_X84Y67.Y Tilo 0.529 u2_core/shared_spi/wb_dat_o<18> u2_core/wb_1master/i_dat_s<29>4 SLICE_X84Y66.G3 net (fanout=1) 0.020 u2_core/wb_1master/i_dat_s<29>4 SLICE_X84Y66.Y Tilo 0.529 u2_core/time_sync/tick_time<30> u2_core/wb_1master/i_dat_s<29>109 SLICE_X86Y62.F3 net (fanout=7) 1.644 u2_core/m0_dat_o<29> SLICE_X86Y62.X Tilo 0.529 u2_core/timer/time_wb<5> u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>112 SLICE_X84Y49.F3 net (fanout=6) 1.013 u2_core/aeMB/aeMB_edk32/rDWBDI<5> SLICE_X84Y49.X Tif5x 0.843 u2_core/pic/mask<3> u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPA_325 u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPA_2_f5_24 SLICE_X82Y48.G1 net (fanout=13) 0.519 u2_core/aeMB/aeMB_edk32/xecu/rOPA<5> SLICE_X82Y48.COUT Topcyg 0.954 u2_core/pic/irq_event<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_lut<5> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.COUT Tbyp 0.104 u2_core/pic/pol<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<6> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.Y Tciny 0.803 u2_core/aeMB/aeMB_edk32/xecu/wADD<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_xor<9> SLICE_X86Y48.G3 net (fanout=1) 0.613 u2_core/aeMB/aeMB_edk32/xecu/wADD<9> SLICE_X86Y48.X Tif5x 0.843 u2_core/pic/pol<17> u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0 SLICE_X104Y49.G3 net (fanout=1) 1.072 N3666 SLICE_X104Y49.Y Tilo 0.529 u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177 R18.O1 net (fanout=1) 1.555 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9> R18.OTCLK1 Tioock 0.651 RAM_A<8> u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 ------------------------------------------------- --------------------------- Total 20.466ns (8.396ns logic, 12.070ns route) (41.0% logic, 59.0% route) -------------------------------------------------------------------------------- Slack (setup path): -0.317ns (requirement - (data path - clock path skew + uncertainty)) Source: u2_core/sys_ram/sys_ram/Mram_ram13.B (RAM) Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF) Requirement: 20.000ns Data Path Delay: 20.317ns (Levels of Logic = 10) Clock Path Skew: 0.000ns Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: u2_core/sys_ram/sys_ram/Mram_ram13.B to u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB16_X0Y16.DOB1 Tbcko 2.082 u2_core/sys_ram/sys_ram/Mram_ram13 u2_core/sys_ram/sys_ram/Mram_ram13.B SLICE_X85Y60.F3 net (fanout=1) 5.492 u2_core/s0_dat_i<13> SLICE_X85Y60.X Tilo 0.479 u2_core/wb_1master/i_dat_s<13>4 u2_core/wb_1master/i_dat_s<13>4 SLICE_X85Y61.F2 net (fanout=1) 0.183 u2_core/wb_1master/i_dat_s<13>4 SLICE_X85Y61.X Tilo 0.479 u2_core/bridge/holding<12> u2_core/wb_1master/i_dat_s<13>109 SLICE_X86Y62.G1 net (fanout=3) 0.798 u2_core/m0_dat_o<13> SLICE_X86Y62.Y Tilo 0.529 u2_core/timer/time_wb<5> u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>4 SLICE_X86Y62.F4 net (fanout=1) 0.014 u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>4/O SLICE_X86Y62.X Tilo 0.529 u2_core/timer/time_wb<5> u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>112 SLICE_X87Y48.F4 net (fanout=6) 0.717 u2_core/aeMB/aeMB_edk32/rDWBDI<5> SLICE_X87Y48.X Tif5x 0.793 u2_core/pic/pol<21> u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_327 u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_26 SLICE_X82Y48.G2 net (fanout=3) 1.098 u2_core/aeMB/aeMB_edk32/xecu/rOPB<5> SLICE_X82Y48.COUT Topcyg 0.954 u2_core/pic/irq_event<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_lut<5> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.COUT Tbyp 0.104 u2_core/pic/pol<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<6> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.Y Tciny 0.803 u2_core/aeMB/aeMB_edk32/xecu/wADD<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_xor<9> SLICE_X86Y48.G3 net (fanout=1) 0.613 u2_core/aeMB/aeMB_edk32/xecu/wADD<9> SLICE_X86Y48.X Tif5x 0.843 u2_core/pic/pol<17> u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0 SLICE_X104Y49.G3 net (fanout=1) 1.072 N3666 SLICE_X104Y49.Y Tilo 0.529 u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177 R18.O1 net (fanout=1) 1.555 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9> R18.OTCLK1 Tioock 0.651 RAM_A<8> u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 ------------------------------------------------- --------------------------- Total 20.317ns (8.775ns logic, 11.542ns route) (43.2% logic, 56.8% route) -------------------------------------------------------------------------------- Slack (setup path): -0.137ns (requirement - (data path - clock path skew + uncertainty)) Source: u2_core/sys_ram/sys_ram/Mram_ram13.B (RAM) Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF) Requirement: 20.000ns Data Path Delay: 20.137ns (Levels of Logic = 10) Clock Path Skew: 0.000ns Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: u2_core/sys_ram/sys_ram/Mram_ram13.B to u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB16_X0Y16.DOB1 Tbcko 2.082 u2_core/sys_ram/sys_ram/Mram_ram13 u2_core/sys_ram/sys_ram/Mram_ram13.B SLICE_X85Y60.F3 net (fanout=1) 5.492 u2_core/s0_dat_i<13> SLICE_X85Y60.X Tilo 0.479 u2_core/wb_1master/i_dat_s<13>4 u2_core/wb_1master/i_dat_s<13>4 SLICE_X85Y61.F2 net (fanout=1) 0.183 u2_core/wb_1master/i_dat_s<13>4 SLICE_X85Y61.X Tilo 0.479 u2_core/bridge/holding<12> u2_core/wb_1master/i_dat_s<13>109 SLICE_X86Y62.G1 net (fanout=3) 0.798 u2_core/m0_dat_o<13> SLICE_X86Y62.Y Tilo 0.529 u2_core/timer/time_wb<5> u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>4 SLICE_X86Y62.F4 net (fanout=1) 0.014 u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>4/O SLICE_X86Y62.X Tilo 0.529 u2_core/timer/time_wb<5> u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>112 SLICE_X87Y48.F4 net (fanout=6) 0.717 u2_core/aeMB/aeMB_edk32/rDWBDI<5> SLICE_X87Y48.X Tif5x 0.793 u2_core/pic/pol<21> u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_327 u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPB_2_f5_26 SLICE_X82Y48.G2 net (fanout=3) 1.098 u2_core/aeMB/aeMB_edk32/xecu/rOPB<5> SLICE_X82Y48.COUT Topcyg 0.774 u2_core/pic/irq_event<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.COUT Tbyp 0.104 u2_core/pic/pol<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<6> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.Y Tciny 0.803 u2_core/aeMB/aeMB_edk32/xecu/wADD<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_xor<9> SLICE_X86Y48.G3 net (fanout=1) 0.613 u2_core/aeMB/aeMB_edk32/xecu/wADD<9> SLICE_X86Y48.X Tif5x 0.843 u2_core/pic/pol<17> u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0 SLICE_X104Y49.G3 net (fanout=1) 1.072 N3666 SLICE_X104Y49.Y Tilo 0.529 u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177 R18.O1 net (fanout=1) 1.555 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9> R18.OTCLK1 Tioock 0.651 RAM_A<8> u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 ------------------------------------------------- --------------------------- Total 20.137ns (8.595ns logic, 11.542ns route) (42.7% logic, 57.3% route) -------------------------------------------------------------------------------- Slack (setup path): -0.084ns (requirement - (data path - clock path skew + uncertainty)) Source: u2_core/sys_ram/sys_ram/Mram_ram13.B (RAM) Destination: u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 (FF) Requirement: 20.000ns Data Path Delay: 20.084ns (Levels of Logic = 10) Clock Path Skew: 0.000ns Source Clock: u2_core/buffer_pool/wb_clk_i rising at 0.000ns Destination Clock: u2_core/buffer_pool/wb_clk_i rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: u2_core/sys_ram/sys_ram/Mram_ram13.B to u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB16_X0Y16.DOB1 Tbcko 2.082 u2_core/sys_ram/sys_ram/Mram_ram13 u2_core/sys_ram/sys_ram/Mram_ram13.B SLICE_X85Y60.F3 net (fanout=1) 5.492 u2_core/s0_dat_i<13> SLICE_X85Y60.X Tilo 0.479 u2_core/wb_1master/i_dat_s<13>4 u2_core/wb_1master/i_dat_s<13>4 SLICE_X85Y61.F2 net (fanout=1) 0.183 u2_core/wb_1master/i_dat_s<13>4 SLICE_X85Y61.X Tilo 0.479 u2_core/bridge/holding<12> u2_core/wb_1master/i_dat_s<13>109 SLICE_X86Y62.G1 net (fanout=3) 0.798 u2_core/m0_dat_o<13> SLICE_X86Y62.Y Tilo 0.529 u2_core/timer/time_wb<5> u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>4 SLICE_X86Y62.F4 net (fanout=1) 0.014 u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>4/O SLICE_X86Y62.X Tilo 0.529 u2_core/timer/time_wb<5> u2_core/aeMB/aeMB_edk32/regf/rDWBDI<5>112 SLICE_X84Y49.F3 net (fanout=6) 1.013 u2_core/aeMB/aeMB_edk32/rDWBDI<5> SLICE_X84Y49.X Tif5x 0.843 u2_core/pic/mask<3> u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPA_325 u2_core/aeMB/aeMB_edk32/xecu/Mmux_rOPA_2_f5_24 SLICE_X82Y48.G1 net (fanout=13) 0.519 u2_core/aeMB/aeMB_edk32/xecu/rOPA<5> SLICE_X82Y48.COUT Topcyg 0.954 u2_core/pic/irq_event<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_lut<5> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<5> SLICE_X82Y49.COUT Tbyp 0.104 u2_core/pic/pol<18> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<6> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.CIN net (fanout=1) 0.000 u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<7> SLICE_X82Y50.Y Tciny 0.803 u2_core/aeMB/aeMB_edk32/xecu/wADD<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_cy<8> u2_core/aeMB/aeMB_edk32/xecu/Madd_AUX_111_addsub0000_xor<9> SLICE_X86Y48.G3 net (fanout=1) 0.613 u2_core/aeMB/aeMB_edk32/xecu/wADD<9> SLICE_X86Y48.X Tif5x 0.843 u2_core/pic/pol<17> u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0_F u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177_SW0 SLICE_X104Y49.G3 net (fanout=1) 1.072 N3666 SLICE_X104Y49.Y Tilo 0.529 u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9_1 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9>177 R18.O1 net (fanout=1) 1.555 u2_core/aeMB/aeMB_edk32/xecu/xRESULT<9> R18.OTCLK1 Tioock 0.651 RAM_A<8> u2_core/aeMB/aeMB_edk32/xecu/rRESULT_9 ------------------------------------------------- --------------------------- Total 20.084ns (8.825ns logic, 11.259ns route) (43.9% logic, 56.1% route) -------------------------------------------------------------------------------- Derived Constraint Report Derived Constraints for TS_clk_fpga_p +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_clk_fpga_p | 10.000ns| 5.987ns| 10.350ns| 0| 1| 6| 2289901| | TS_dcm_out | 10.000ns| 9.974ns| N/A| 0| 0| 467329| 0| | TS_clk_div | 20.000ns| 20.699ns| N/A| 1| 0| 1822572| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ 1 constraint not met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock GMII_RX_CLK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ GMII_RX_CLK | 7.837| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock clk_fpga_n ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_fpga_n | 20.699| 2.901| 4.791| | clk_fpga_p | 20.699| 2.901| 4.791| | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock clk_fpga_p ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_fpga_n | 20.699| 2.901| 4.791| | clk_fpga_p | 20.699| 2.901| 4.791| | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock clk_to_mac ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_to_mac | 7.909| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock cpld_clk ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ cpld_clk | 7.390| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ser_rx_clk ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ ser_rx_clk | 6.747| | | | ---------------+---------+---------+---------+---------+ Timing summary: --------------- Timing errors: 1 Score: 699 (Setup/Max: 699, Hold: 0) Constraints cover 2324598 paths, 0 nets, and 87669 connections Design statistics: Minimum period: 20.699ns (Maximum frequency: 48.312MHz) Maximum path delay from/to any node: 9.867ns Analysis completed Fri May 14 16:11:08 2010 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 307 MB