Re: [Discuss-gnuradio] Minimum external clock for FPGA?

[sandeep mishra]

Hi,
Please help.
during installation of ariprobe I got following errors:

out_pcap.c:8:18: error: pcap.h: No such file or directory
out_pcap.c: In function ‘write_pcap_file_header’:
out_pcap.c:34: error: storage size of ‘pfh’ isn’t known
out_pcap.c:37: error: ‘PCAP_VERSION_MAJOR’ undeclared (first use in this function)
out_pcap.c:37: error: (Each undeclared identifier is reported only once
out_pcap.c:37: error: for each function it appears in.)
out_pcap.c:38: error: ‘PCAP_VERSION_MINOR’ undeclared (first use in this function)
out_pcap.c: In function ‘write_pcap_packet’:
out_pcap.c:104: warning: incompatible implicit declaration of built-in function ‘memcpy’
make[4]: *** [out_pcap.lo] Error 1
make[4]: Leaving directory `/home/sandeep/airprobe/gsm-tvoid/src/lib'
make[3]: *** [all] Error 2
make[3]: Leaving directory `/home/sandeep/airprobe/gsm-tvoid/src/lib'
make[2]: *** [all-recursive] Error 1
make[2]: Leaving directory `/home/sandeep/airprobe/gsm-tvoid/src'
make[1]: *** [all-recursive] Error 1
make[1]: Leaving directory `/home/sandeep/airprobe/gsm-tvoid'
make: *** [all] Error 2
address@hidden:~/airprobe/gsm-tvoid$ 

I am using ubantu 9.1(karmic), gnuradio-3.2.2 and airprobe is installed via git.
Kindly help me please

On Mon, Jan 18, 2010 at 8:31 AM, John Orlando <address@hidden> wrote:

It is my understanding that the current FPGA image used for OpenBTS will fail on the transmit side if the FPGA clock is slower than the USB clock.  The USB clock is 48 MHz.

If you (or anyone else involved) can provide the details of what the issue is here, I may have some time to dive in and potentially come up with a fix.  Let me know if interested.
 

Also, the GSM symbol clock is derived from 13 MHz, so if you use a multiple-of-13 clock, you can simplify a lot of the decimation.

These two facts together led us to choose 52 MHz for the current OpenBTS USRP clock.

Gotcha.  Thanks for the quick response David.

Anyone else know of any other issues that would prevent the FPGA from being clocked at lower speeds?

On Jan 16, 2010, at 4:33 PM, John Orlando wrote:

Hi all,
I've seen posts about folks providing an external clock of 44 MHz to the USRP, and with a few software tweaks, getting it to work.  I'm wondering if there is a floor as to how low this clock be reduced without causing problems.  I know some A/D converters have minimum sample rates, but the AD9862 datasheet doesn't seem to indicate that it does.  Is there any reason I couldn't run my USRP with an external reference at 26 MHz?  How 'bout 10 MHz?

The only datapoint I could find was a reference to the fact that the current openBTS FPGA image doesn't run (?) at 26 MHz due to a "firmware fix" that is needed, though I'm guessing that is referencing the FPGA code:

http://www.mail-archive.com/address@hidden/msg21130.html

I'll probably make the USRP hardware modification on Monday to try these out with an external sig gen, but I figured I'd throw the question to the list prior to that to see if I could get a definitive answer.

Thanks much...

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Regards,
John Orlando
CEO/System Architect
Epiq Solutions
www.epiq-solutions.com

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David A. Burgess

Kestrel Signal Processing, Inc.

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Regards,
John Orlando
CEO/System Architect
Epiq Solutions
www.epiq-solutions.com

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Thanks.....