[Discuss-gnuradio] USRP Rev4 FX2 firmware question. Initializing FIFOs ?

[Ryan Seal]

I have been working on modifications to the USRP board so that I can pass  
a gating signal through the basic RX daughterboard to gate signal  
collection for a pulsed radar application. This is somewhat working, but I  
am having problems with data alignment when stopping and starting the  
system. It appears that the FX2 chip does not clear its fifo when  
stopping/starting the system. There seems to be an arbitrary number of  
data samples left in the buffers when I restart the system, and this  
causes sample 0 to appear at sample X. Is there a function I can call to  
manually wipe the FX2 fifos and ensure that they are empty when starting  
the system? If not, what do I need to do to resolve this; possibly  
customize the firmware (this looks like a headache)?

The FPGA modifications appear to work as expected. These buffers are  
definitely zeroed upon restart. I have verified most of this by routing  
important signals through the headers on the dboards to a logic analyzer.  
Everything looks pretty good from the FPGA's perspective.

Thanks,
Ryan


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