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From: | Paul Creekmore |
Subject: | Re: [Discuss-gnuradio] Purpose of extra two bits sent to FX2 chip with data samples |
Date: | Mon, 02 Feb 2009 00:51:48 -0500 |
User-agent: | Thunderbird 2.0.0.19 (Windows/20081209) |
Eric Blossom wrote:
Hmm... no, I don't think we're talking about the same thing. I'm, looking at usrp/fpga/sdr_lib/rx_buffer.v, lines 90 and 97. Here's an excerpt:On Sun, Feb 01, 2009 at 12:30:58AM -0500, Paul Creekmore wrote:The FPGA on USRP1 sends an extra two bits of data with each 16-bit word (to the FX2 chip). If I'm not mistaken, the first bit is set when accompanying a sample from rx channel 0, and the second bit is set when accompanying an inphase (as opposed to quadrature) sample (presumably from channels 0, 2, 4, or 6). * What significance do these two bits have in the handling of the data after the FPGA? I'm trying to figure out how best to set these bits in the case of packed samples at lower quantization levels. Thanks, PaulUhh, what two extra bits? The GPIF bus is 16-bits wide... The FPGA does report two status bits (independent of the data bits) that indicate whether (1) it has room for a new packet from the FX2 and (2) if it has a packet available for the FX2. I don't think anything you're doing should have anything to do with how those flags are generated. Did this help? Eric 88 fifo_4k_18 rxfifo 89 ( // DSP Write Side 90 .data ( {ch0_in, phase[0], fifodata} ), 91 .wrreq (~rx_full & (phase != 0)), 92 .wrclk ( rxclk ), 93 .wrfull ( rx_full ), 94 .wrempty ( ), 95 .wrusedw ( ), 96 // USB Read Side 97 .q ( {ch0_out,iq_out,usbdata} ), 98 .rdreq ( RD & ~read_count[8] ), 99 .rdclk ( ~usbclk ), 100 .rdfull ( ), 101 .rdempty ( ), 102 .rdusedw ( rxfifolevel ), 103 // Async, shared 104 .aclr ( reset ) ); This is the port mapping for the receive fifo. The fifo is 18 bits wide, and "ch0_in" and "phase[0]" are concatenated with the 16-bit data word to form the input to the fifo. --Paul |
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