Re: [Discuss-gnuradio] Upgrade (downgrade?) to a Q6600 CPU

[Johnathan Corgan]

On Sat, Dec 27, 2008 at 3:25 PM, Jing Cao <address@hidden> wrote:

> Can we implement some block in FPGA to reduce the CPU consumption?
>
> Have any work like this done already ?

This has been done in a variety of ways for the USRP1, although there
isn't much space free in the FPGA for new logic unless you are willing
to sacrifice transmit capability or the number of receiver DDCs.

The USRP2 has a much larger amount of free logic (~50% currently, may
change) and was designed with the idea that people might offload the
high rate portions of the signal processing chain, or even all of it,
and run hostless.

Of course, the effort to write HDL, verify in simulation, verify in
synthesis, and debug with a logic analyzer is lot more than assembling
blocks into a flowgraph in Python.

-Johnathan