[Discuss-gnuradio] Re: USRP2 expansion interface

[Matt Ettus]

address@hidden wrote:
> Hi,
>
> I'm Kevin Bobrowski. I am currently doing research with GNUradio, USRP,
> and soon the USRP2 at Worcester Polytechnic Institute.  A while back, I
> noticed that there was an expansion port.  I and along with others in my
> lab would like to interface to this port to connect the USRP2 to a Virtex
> 5 SXT eval board.  I am looking for any documentation concerning this
> port, especially how it is tied into the the FPGA, if that is the case. 
> Can you also provide details concerning the debug port?
>
>   


The expansion port is pretty straightforward.  It uses a serial-attached 
SCSI (mini-SAS) cable.  The cable has 4 lanes.  Each lane consists of 1 
differential pair input and 1 differential pair output.  All lanes are 
AC (capacitor) coupled.  The 4 lanes are allocated as follows:

1 - High-speed SERDES, 2 gbps 8B10B encoded.  This interface is handled 
by a TLK2701 from TI, and it connects to the FPGA.  You should be able 
to connect this interface to the RocketIO GTP/GTX transceivers on the 
virtex 5.  Also, see the usrp2/fpga/serdes directory in the SVN 
repository to see how we handle the interface and protocol, framing, and 
flow control.

2 - 10 MHz clock reference

3 - Digital IO, connected directly to LVDS IOs on the FPGA.  We 
currently have this set up to do time syncing, but you can do whatever 
you like with it.

4 - Unused


Matt