[Discuss-gnuradio] Decimation questions

[Sebastiaan Heunis]

Hi

I would like to ask some questions about the rx chain in the FPGA.

The following Verilog code is found in the rx_chain.v Verilog file

##################################################

phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
     (.clk(clock),.reset(reset),.enable(enable),
      
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
      .strobe(sample_strobe),.phase(phase) );

##################################################

and in usrp_std.v this is found for the first rx_chain

##################################################

rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
     ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
       
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
       
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
       
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));

##################################################

from the above FR_RX_FREQ_0 and FR_RX_PHASE_0 is passed to the
phase_acc which is used for the cordic algorithm.  I know that
FR_RX_FREQ_0 holds the value of the DDC center frequency and
FR_RX_PHASE_0 holds the starting phase value.

Now I would like to know if anyone could please help me with the following:

1.  When we use a tv_rx daughterboard, the FR_RX_FREQ_0 value is set
to -20MHZ, right?  From what I know it seems as if the Microtune
module mixes the signal down to 20MHz.
2.  Where does FR_RX_PHASE_0 come from?  Is this 0 because we start on
the x axis with zero degrees phase when using the cordic algorithm?
3.  sample_strobe gets set to 1 in master_control.v?  decimator_strobe
is a pulse signal with 64MHz/(decimation_rate-1) pulses per second?  I
assume that this has something to do with the rate changer in the CIC
filter that drops the sampling rate from 64MHz.  I would just like to
know why we use rate-1 in the strobe generator part in master_control?

I'm just a little confused with the strobe signals.  Logic tells me
that if we're decimating by 16, we have a decimation of 8 in the CIC
and 2 in the HBF, so strobe_decim should be 64MHz/8 and hb_strobe
should be 64MHz/(8*2).

Thank you in advance.

Sebastiaan Heunis