Re: [Discuss-gnuradio] Algorithm RSSI on FPGA

[George Nychis]

Hi,

It's very simple.

Take a look at the Verilog FPGA code:
http://gnuradio.org/trac/browser/gnuradio/trunk/usrp/fpga/sdr_lib/rssi.v

I actually think it's masking out 2^-11 by default.

See everywhere where it has [25:10] ... this means that it is masking 
out the bottom 11 bits (10,9,8..0).  If you want it to be 2^-10, change 
all the [25:10] to [25:9].

Then, rebuild.

- George


address@hidden wrote:
> Hi,
> I'm working on RSSI value and reading mailing lists I have understood how RSSI
> is calculated. In the algorithm of RSSI in verilog alpha value is 2^-10 because
> the shift is made on 10 bits. I want to change alpha value (decrease or
> increase) but I don't understand how I can change it in the algorithm in
> verilog. Could you help me?
>
> Thank you very much.
>
>
>
>
>
>
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