[Discuss-gnuradio] not gnuradio, but FPGA

[Brett L. Trotter]

I realize that this is not gnuradio traffic specifically, hopfully it
won't put anybody off- I apologize if it does, but I'm desperate!
I'm working with an Altera/Terasic DE2 board trying to get ethernet up
and running with the onboard DM9000a. I've read the manuals backwards
and forwards and I don't see much about what really happens in 16-bit
mode (the way I understand it, since the EE* pins are unconnected on the
DE2, we're in 16-bit mode and all of the pins are labeled
ENET_DATA[15..0]. In any case I have a huge chunk of a state machine
that should have me getting all linked up but is failing to do so. The
simulation looks perfect as far as I can tell from my understanding of
the documentation. If anyone out there is really familiar with the DE2
and/or the Davicom DM9000a or just is willing to help, I'll send over
all of my quartus project files (in VHDL)

Thanks in advance!

P.S. Sooner or later, I may understand enough to make some level of
contribution on the Verilog code- or perhaps port it to VHDL. It has
been too long since my last patch.