On Wed, Oct 10, 2007 at 06:07:04PM -0400, address@hidden wrote:
Ok, that works in principle, but I'm finding that I cannot sustain the
same data rate as before on a fast dual core machine.
I'm acquiring all 4 channels, and I'm doing both low-pass and high-pass
filtering on all of them. I am also displaying 5 sinks simultaneously; 1
fft and 4 scopes.
You'll most likely find that the bulk of your cycles are spent in the
gui. Try disabling it.
So, in the long term it would help to have this sorted out in the fpga if
that's possible; is that impossible as things stand now, or is there
sufficient space in the 4rx no hb fpga?
IIRC, the std_4rx_0tx.rbf configuration uses about 86% of the FPGA.
Eric