Re: [Discuss-gnuradio] several beginner questions (mostly about the fpga)

[Brian Padalino]

On 6/14/07, micael magpayo <address@hidden> wrote:
> Hello GNURadio community,
> I'm really interested in the GNURadio project and I want to have a better
> understanding of the FPGA code (usrp_std.v etc...). I've been trying to
> learn it on my own but some parts are hard to understand when all you have
> is the source code. So here I am and here are my questions.
>
> - What are the following signals for? (in rx_chain.v)
>    -sample_strobe.v
>    -decimator_strobe.v
>    -hb_strobe.v
>    -serial_addr,serial_data,serial_strobe
>    -debugdata,debugctrl

sample_strobe follows the full speed samples coming from the ADC and
feeds the input of the decimating CIC filter.

decimator_strobe is generated by the decimating CIC filter to feed the
samples into the halfband FIR filter at the specified and decimated
rate.

When the decimation by N takes place, you get a sample 1/N cycles.
This ratio is preserved throughout that part of the chain.

The hb_strobe comes out of the halfband decimating FIR filter.  This
is a constant decimation by 2, but is asserted when the FIR filter has
an output to pass out of the RX chain.

serial_* is the interface used for register writing.  If you want to
modify any of the registers within the module, the simple serial
interface from the FX2 -> FPGA is what changes them.  In this case,
they are used to modify the register for phase accumulation within the
FPGA for the cordic.

debug* is just used for debug as the name suggests.  In the current
implementation in the trunk, it looks like the input to the halfband
FIR filter is what is output on the debug bus.

> -How many clock cycles does it take the cordic module to output valid data
> and why is the cordic algorithm implemented (in cordic.v) fixed at 12
> iterations?

It is a pipelined module which takes samples at the full rate and
through 12 pipeline stages outputs the rotated vector.  Why 12 was
picked is probably a size issue since you create registers and flops
for each stage.  You can make the pipeline deeper, and even variable
if you want.  There is a TODO in there which suggests making it a
variable length - not sure if the comment means at runtime or at
buildtime, but have a go at it.

> Sorry if my questions have already been asked or if they are easy to answer.
> If someone can point me to right direction, I would gladly learn it by
> myself. So far I've only read the source code. Are there any other sources
> that can answer my questions?

It's probably good to just discuss them anyway.  The FPGA seems to be
a place where a lot of the black magic happens, but it really isn't
all that complicated at all.

I believe I am correct, but if anyone else has anything to add or
correct - please feel free.

Brian