[Discuss-gnuradio] FX2 TX DMA Transfer Question

[Brian Padalino]

When the FX2 detects the have_space pin on the FPGA, does it transfer
1 entire buffered USB packet to the FPGA, then re-check the have_space
pin?

Would it be reasonable to assume a 1 clock delay between the last byte
of one 512-byte packet being written to the FPGA and the first byte of
a second 512-byte packet being written to the FPGA?

Thanks,
Brian