[Discuss-gnuradio] Re: USB FIFO

[Thibaud Hottelier]

Brian Padalino wrote:
> On 3/29/07, Thibaud Hottelier <address@hidden> wrote:
> > My idea was that the process in the fpga that read usb_bus can store the
> > packet and the total length is reached, ignore the data coming because
> > we know its padding. That process is the first process in the wiki page
> > (http://gnuradio.org/trac/wiki/UsrpTxModifications). This way we don't
> > need a dual clock fifo that can skip, only a single clock one.
>
> We need a dual clocked FIFO just because the FX2 is running on a
> different clock domain than the FPGA.  The FPGA runs at 64MHz whereas
> the FX2 runs at something like 24MHz I believe.  Because these clocks
> know nothing about each other - their domains need a nice handoff
> point like that dual clocked FIFO.
>
> For a handy reference:
>    http://www.fpga4fun.com/clocks.html
>
> If you don't understand, we'll have to talk it over some more.  It's a
> good concept to understand and surely will help in the future.

"This way we don't
need a dual clock fifo that can skip, only a single clock one"
Yes, that's wrong, I wanted to say that we need only standard dual clock 
fifo or single clock fifo that can skip packets but we don't need a dual 
clock fifo that can skip.

Thibaud

> Brian