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Re: [Discuss-gnuradio] Using RFX2400 from C++
|
From: |
Dan Halperin |
|
Subject: |
Re: [Discuss-gnuradio] Using RFX2400 from C++ |
|
Date: |
Sun, 14 Jan 2007 20:00:07 -0800 |
|
User-agent: |
Thunderbird 1.5.0.9 (X11/20070103) |
I decided to take the path of least resistance and instrumented usrp1.py
to print whenever a set_* or write_* function was called. I then ran a
modified version of tunnel.py to get the following output (full output
attached as log):
<snip>
_write_oe (<gr_block usrp1_sink_c (0)>, 0, 0, 65535)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 40, 0)
set_pga (<gr_block usrp1_sink_c (0)>, 0, 0.0)
set_pga (<gr_block usrp1_sink_c (0)>, 1, 0.0)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 20, 0)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 21, 0)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 22, 0)
</snip>
I then took this output, grepped for source, and turned it into C code
(attached), but have been unable to get signal out. Interestingly, when
I screwed up and used the sink instead (that should be the transmit
path, right?), I did get signal out, albeit not pretty sine waves like I
expected (the signal was sent using usrp_siggen at the same freq with -w
0). I'm confused.
Also, I may be doing that thing with the write_spi wrong, I don't know
how to properly handle the \x00s.
//
-Dan
_write_oe (<gr_block usrp1_sink_c (0)>, 0, 0, 65535)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 40, 0)
set_pga (<gr_block usrp1_sink_c (0)>, 0, 0.0)
set_pga (<gr_block usrp1_sink_c (0)>, 1, 0.0)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 20, 0)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 21, 0)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 22, 0)
_write_oe (<gr_block usrp1_sink_c (0)>, 0, 224, 65535)
_write_io (<gr_block usrp1_sink_c (0)>, 0, -129, 224)
set_interp_rate (<gr_block usrp1_sink_c (0)>, 320)
set_mux (<gr_block usrp1_sink_c (0)>, 152)
_write_spi (<gr_block usrp1_sink_c (0)>, 0, 16, 0, '4\x00A')
_write_spi (<gr_block usrp1_sink_c (0)>, 0, 16, 0, 'O\xc9$')
_write_spi (<gr_block usrp1_sink_c (0)>, 0, 16, 0, '\x00&&')
set_tx_freq (<gr_block usrp1_sink_c (0)>, 0, -6000000.0)
set_pga (<gr_block usrp1_sink_c (0)>, 0, 0.0)
set_pga (<gr_block usrp1_sink_c (0)>, 1, 0.0)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 20, 96)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 21, 32)
_write_fpga_reg (<gr_block usrp1_sink_c (0)>, 22, 64)
_write_oe (<gr_block usrp1_source_c (7)>, 0, 0, 65535)
_write_fpga_reg (<gr_block usrp1_source_c (7)>, 41, 0)
write_aux_dac (<gr_block usrp1_source_c (7)>, 0, 0, 691)
set_pga (<gr_block usrp1_source_c (7)>, 0, 0)
set_pga (<gr_block usrp1_source_c (7)>, 1, 0)
_write_fpga_reg (<gr_block usrp1_source_c (7)>, 23, 0)
_write_fpga_reg (<gr_block usrp1_source_c (7)>, 24, 0)
_write_fpga_reg (<gr_block usrp1_source_c (7)>, 25, 0)
_write_oe (<gr_block usrp1_source_c (7)>, 0, 224, 65535)
_write_io (<gr_block usrp1_source_c (7)>, 0, -129, 224)
_write_io (<gr_block usrp1_source_c (7)>, 0, 0, 64)
set_adc_buffer_bypass (<gr_block usrp1_source_c (7)>, 0, True)
set_adc_buffer_bypass (<gr_block usrp1_source_c (7)>, 1, True)
set_adc_buffer_bypass (<gr_block usrp1_source_c (7)>, 2, True)
set_adc_buffer_bypass (<gr_block usrp1_source_c (7)>, 3, True)
set_adc_buffer_bypass (<gr_block usrp1_source_c (7)>, 2, True)
set_adc_buffer_bypass (<gr_block usrp1_source_c (7)>, 3, True)
set_decim_rate (<gr_block usrp1_source_c (7)>, 160)
set_mux (<gr_block usrp1_source_c (7)>, 1)
_write_spi (<gr_block usrp1_source_c (7)>, 0, 32, 0, '4\x00A')
_write_spi (<gr_block usrp1_source_c (7)>, 0, 32, 0, 'O\xc9$')
_write_spi (<gr_block usrp1_source_c (7)>, 0, 32, 0, '\x00&\x1e')
set_rx_freq (<gr_block usrp1_source_c (7)>, 0, -2000000.0)
write_aux_dac (<gr_block usrp1_source_c (7)>, 0, 0, 691)
set_pga (<gr_block usrp1_source_c (7)>, 0, 0)
set_pga (<gr_block usrp1_source_c (7)>, 1, 0)
_write_fpga_reg (<gr_block usrp1_source_c (7)>, 23, 32)
_write_fpga_reg (<gr_block usrp1_source_c (7)>, 24, 0)
_write_fpga_reg (<gr_block usrp1_source_c (7)>, 25, 32)
modulation: dbpsk
freq: 2.462G
bitrate: 200kb/sec
samples/symbol: 2
interp: 320
decim: 160
Carrier sense threshold: 30 dB
set_detail (<gr_block usrp1_sink_c (0)>,
<gnuradio.gr.gnuradio_swig_python.gr_block_detail_sptr; proxy of <Swig Object
of type 'gr_block_detail_sptr *' at 0x82c0b50> >)
set_detail (<gr_block usrp1_source_c (7)>,
<gnuradio.gr.gnuradio_swig_python.gr_block_detail_sptr; proxy of <Swig Object
of type 'gr_block_detail_sptr *' at 0x82c9e48> >)
Starting service
/* -*- c++ -*- */
/*
* Copyright 2003,2006 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <usb.h> /* needed for usb functions */
#include <getopt.h>
#include <assert.h>
#include <math.h>
#include "usrp_standard.h"
#include "usrp_bytesex.h"
static bool read_data (usrp_standard_rx *urx, FILE *fp);
static void
usage (char* prog_name)
{
fprintf (stderr, "usage: %s [-l] [-c] [-d <decim>] [-f freq] [-o
output_file]\n", prog_name);
fprintf (stderr, " [-8] 8-bit samples across USB\n");
fprintf (stderr, " [-B <fusb_block_size>] set fast usb block_size\n");
fprintf (stderr, " [-N <fusb_nblocks>] set fast usb nblocks\n");
exit (1);
}
static void
die (const char *msg)
{
fprintf (stderr, "die: %s\n", msg);
exit (1);
}
int
main (int argc, char **argv)
{
bool width_8_p = false;
int ch;
char *output_filename = 0;
int which_board = 0;
int decim = 8; // 32 MB/sec
double center_freq = 0;
int fusb_block_size = 0;
int fusb_nblocks = 0;
int mode = 0;
while ((ch = getopt (argc, argv, "o:d:f:8B:N:W:")) != EOF)
{
switch (ch)
{
case '8':
width_8_p = true;
break;
case 'o':
output_filename = optarg;
break;
case 'd':
decim = strtol (optarg, 0, 0);
break;
case 'f':
center_freq = strtod (optarg, 0);
break;
case 'B':
fusb_block_size = strtol (optarg, 0, 0);
break;
case 'N':
fusb_nblocks = strtol (optarg, 0, 0);
break;
case 'W':
which_board = strtol(optarg, 0, 0);
break;
default:
usage (argv[0]);
}
}
FILE *fp = 0;
if (output_filename)
{
fp = fopen (output_filename, "wb");
if (fp == 0)
perror (output_filename);
}
usrp_standard_rx *urx =
usrp_standard_rx::make (which_board, decim, 1, -1, mode,
fusb_block_size, fusb_nblocks);
if (urx->daughterboard_id (which_board) == -1)
die("No RX daughterboard found.\n");
if (urx == 0)
die ("usrp_standard_rx::make");
if (!urx->set_rx_freq (0, center_freq))
die ("urx->set_rx_freq");
if (width_8_p)
{
int width = 8;
int shift = 8;
bool want_q = true;
if (!urx->set_format(usrp_standard_rx::make_format(width, shift,
want_q)))
die("urx->set_format");
}
//
printf("Turning off all outputs via write_oe.\n");
if (!urx->_write_oe(0, 0, 0xffff))
die("Turning off all outputs vie write_oe.");
//
printf("_write_fpga_reg (<gr_block usrp1_source_c (7)>, 41, 0)\n");
if (!urx->_write_fpga_reg(41, 0))
die("_write_fpga_reg (<gr_block usrp1_source_c (7)>, 41, 0)");
//
printf("write_aux_dac (<gr_block usrp1_source_c (7)>, 0, 0, 691)\n");
if (!urx->write_aux_dac (0, 0, 691))
die("write_aux_dac (<gr_block usrp1_source_c (7)>, 0, 0, 691)");
//
printf("set_pga (<gr_block usrp1_source_c (7)>, 0, 0)\n");
if (!urx->set_pga (0, 0))
die("set_pga (<gr_block usrp1_source_c (7)>, 0, 0)");
//
printf("set_pga (<gr_block usrp1_source_c (7)>, 1, 0)\n");
if (!urx->set_pga (1, 0))
die("set_pga (<gr_block usrp1_source_c (7)>, 1, 0)");
//
printf("_write_fpga_reg (<gr_block usrp1_source_c (7)>, 23, 0)\n");
if (!urx->_write_fpga_reg(23, 0) || !urx->_write_fpga_reg(24, 0) ||
!urx->_write_fpga_reg(25, 0))
die("_write_fpga_reg (<gr_block usrp1_source_c (7)>, 23, 0)");
//
printf("_write_oe (<gr_block usrp1_source_c (7)>, 0, 224, 65535)\n");
if (!urx->_write_oe(0, 224, 65535))
die("_write_oe (<gr_block usrp1_source_c (7)>, 0, 224, 65535)");
printf("_write_io (<gr_block usrp1_source_c (7)>, 0, -129, 224)\n");
if (!urx->write_io (0, -129, 224))
die("_write_io (<gr_block usrp1_source_c (7)>, 0, -129, 224)");
printf("_write_io (<gr_block usrp1_source_c (7)>, 0, 0, 64)\n");
if (!urx->write_io (0, 0, 64))
die("_write_io (<gr_block usrp1_source_c (7)>, 0, 0, 64)");
printf("set_adc_buffer_bypass (<gr_block usrp1_source_c (7)>, 0, True)\n");
if (!urx->set_adc_buffer_bypass (0, true)
|| !urx->set_adc_buffer_bypass (1, true)
|| !urx->set_adc_buffer_bypass (2, true)
|| !urx->set_adc_buffer_bypass (3, true)
|| !urx->set_adc_buffer_bypass (2, true)
|| !urx->set_adc_buffer_bypass (3, true))
die("set_adc_buffer_bypass (<gr_block usrp1_source_c (7)>, 0, True)");
// printf("set_decim_rate (<gr_block usrp1_source_c (7)>, 160)\n");
// if (!urx->set_decim_rate(160))
// die("set_decim_rate (<gr_block usrp1_source_c (7)>, 160)");
// printf("set_mux (<gr_block usrp1_source_c (7)>, 1)\n");
// if (!urx->set_mux(1))
// die("set_mux (<gr_block usrp1_source_c (7)>, 1)");
printf("_write_spi (<gr_block usrp1_source_c (7)>, 0, 32, 0, '4\x00A')\n");
if (!urx->_write_spi(0, 32, 0, "4\x00A"))
die("_write_spi (<gr_block usrp1_source_c (7)>, 0, 32, 0, '4\x00A')");
printf("_write_spi (<gr_block usrp1_source_c (7)>, 0, 32, 0, '4\xc9$')\n");
if (!urx->_write_spi(0, 32, 0, "4\xc9$"))
die("_write_spi (<gr_block usrp1_source_c (7)>, 0, 32, 0, '4\xc9$')");
// printf("_write_spi (<gr_block usrp1_source_c (7)>, 0, 32, 0,
'\\x00&\x1e')\n");
// if (!urx->_write_spi(0, 32, 0, "\x00&\x1e"))
// die("_write_spi (<gr_block usrp1_source_c (7)>, 0, 32, 0,
'\x00&\x1e')");
// if(!urx->set_rx_freq(0, -2000000.0))
// die("set_rx_freq");
printf("write_aux_dac (<gr_block usrp1_source_c (7)>, 0, 0, 691)\n");
if (!urx->write_aux_dac(0, 0, 691))
die("write_aux_dac (<gr_block usrp1_source_c (7)>, 0, 0, 691)");
//
printf("set_pga (<gr_block usrp1_source_c (7)>, 0, 0)\n");
if (!urx->set_pga (0, 0))
die("set_pga (<gr_block usrp1_source_c (7)>, 0, 0)");
//
printf("set_pga (<gr_block usrp1_source_c (7)>, 1, 0)\n");
if (!urx->set_pga (1, 0))
die("set_pga (<gr_block usrp1_source_c (7)>, 1, 0)");
//
printf("_write_fpga_reg (<gr_block usrp1_source_c (7)>, 23, 32)\n");
if (!urx->_write_fpga_reg(23, 32) || !urx->_write_fpga_reg(24, 0) ||
!urx->_write_fpga_reg(25, 32))
die("_write_fpga_reg (<gr_block usrp1_source_c (7)>, 23, 32)");
// Back to reality
printf("PGA min: %lf PGA max: %lf PGA step: %lf\n", urx->pga_min(),
urx->pga_max(), urx->pga_db_per_step());
printf("Setting gain to maximum %lf\n", urx->pga_max());
if (!urx->set_pga(0, urx->pga_max()))
die("urx->set_pga");
if (!urx->set_pga(1, urx->pga_max()))
die("urx->set_pga");
urx->start(); // start data xfers
read_data (urx, fp);
if (fp)
fclose (fp);
delete urx;
return 0;
}
static bool
read_data (usrp_standard_rx *urx, FILE *fp)
{
int fd = -1;
static const unsigned int BUFSIZE = urx->block_size();
static const unsigned int N = BUFSIZE/sizeof (short);
short buf[N];
printf("BUFSIZE is %d, N = %d\n", BUFSIZE, N);
if (fp)
fd = fileno (fp);
bool overrun;
int noverruns = 0;
int state = 0;
unsigned int byte = 0;
while (1)
{
unsigned int ret = urx->read (buf, sizeof (buf), &overrun);
if (ret != sizeof (buf))
{
fprintf (stderr, "test_input: error, ret = %d\n", ret);
}
if (overrun)
{
printf ("rx_overrun\n");
noverruns++;
state = 0;
byte = 0;
continue;
}
unsigned int count = 0;
for (unsigned int i = 0; i < N; ++i)
{
if (buf[i] > 3000 || buf[i] < -3000)
++count;
}
// printf("Count: %d\n", count);
if (state < 5)
{
if (count > N/8)
{
++state;
printf("State is %u\n", state);
}
else
state = 0;
}
else if (state == 13)
{
state = 0;
fprintf(stderr, "Got byte %u\n", byte);
byte = 0;
if (count > N/4)
++state;
}
else
{
byte <<= 1;
if (count > N/8)
byte |= 1;
++state;
}
if (fd != -1)
{
// for (unsigned int i = 0; i < N; ++i)
// buf[i] = usrp_to_host_short (buf[i]);
// if (write (fd, buf, sizeof (buf)) == -1)
// {
// perror ("write");
// fd = -1;
// }
fwrite(buf, sizeof(buf[0]), N, fp);
}
}
printf ("noverruns = %d\n", noverruns);
return true;
}
# This file was automatically generated by SWIG (http://www.swig.org).
# Version 1.3.31
#
# Don't modify this file, modify the SWIG interface instead.
import _usrp1
import new
new_instancemethod = new.instancemethod
try:
_swig_property = property
except NameError:
pass # Python < 2.2 doesn't have 'property'.
def _swig_setattr_nondynamic(self,class_type,name,value,static=1):
if (name == "thisown"): return self.this.own(value)
if (name == "this"):
if type(value).__name__ == 'PySwigObject':
self.__dict__[name] = value
return
method = class_type.__swig_setmethods__.get(name,None)
if method: return method(self,value)
if (not static) or hasattr(self,name):
self.__dict__[name] = value
else:
raise AttributeError("You cannot add attributes to %s" % self)
def _swig_setattr(self,class_type,name,value):
return _swig_setattr_nondynamic(self,class_type,name,value,0)
def _swig_getattr(self,class_type,name):
if (name == "thisown"): return self.this.own()
method = class_type.__swig_getmethods__.get(name,None)
if method: return method(self)
raise AttributeError,name
def _swig_repr(self):
try: strthis = "proxy of " + self.this.__repr__()
except: strthis = ""
return "<%s.%s; %s >" % (self.__class__.__module__,
self.__class__.__name__, strthis,)
import types
try:
_object = types.ObjectType
_newclass = 1
except AttributeError:
class _object : pass
_newclass = 0
del types
def _swig_setattr_nondynamic_method(set):
def set_attr(self,name,value):
if (name == "thisown"): return self.this.own(value)
if hasattr(self,name) or (name == "this"):
set(self,name,value)
else:
raise AttributeError("You cannot add attributes to %s" % self)
return set_attr
SPI_FMT_xSB_MASK = _usrp1.SPI_FMT_xSB_MASK
SPI_FMT_LSB = _usrp1.SPI_FMT_LSB
SPI_FMT_MSB = _usrp1.SPI_FMT_MSB
SPI_FMT_HDR_MASK = _usrp1.SPI_FMT_HDR_MASK
SPI_FMT_HDR_0 = _usrp1.SPI_FMT_HDR_0
SPI_FMT_HDR_1 = _usrp1.SPI_FMT_HDR_1
SPI_FMT_HDR_2 = _usrp1.SPI_FMT_HDR_2
SPI_ENABLE_FPGA = _usrp1.SPI_ENABLE_FPGA
SPI_ENABLE_CODEC_A = _usrp1.SPI_ENABLE_CODEC_A
SPI_ENABLE_CODEC_B = _usrp1.SPI_ENABLE_CODEC_B
SPI_ENABLE_reserved = _usrp1.SPI_ENABLE_reserved
SPI_ENABLE_TX_A = _usrp1.SPI_ENABLE_TX_A
SPI_ENABLE_RX_A = _usrp1.SPI_ENABLE_RX_A
SPI_ENABLE_TX_B = _usrp1.SPI_ENABLE_TX_B
SPI_ENABLE_RX_B = _usrp1.SPI_ENABLE_RX_B
FPGA_MODE_NORMAL = _usrp1.FPGA_MODE_NORMAL
FPGA_MODE_LOOPBACK = _usrp1.FPGA_MODE_LOOPBACK
FPGA_MODE_COUNTING = _usrp1.FPGA_MODE_COUNTING
class usrp1_sink_base(object):
"""Proxy of C++ usrp1_sink_base class"""
thisown = _swig_property(lambda x: x.this.own(), lambda x, v:
x.this.own(v), doc='The membership flag')
def __init__(self): raise AttributeError, "No constructor defined"
__repr__ = _swig_repr
__swig_destroy__ = _usrp1.delete_usrp1_sink_base
__del__ = lambda self : None;
def set_interp_rate(*args):
"""set_interp_rate(self, unsigned int rate) -> bool"""
print "set_interp_rate", args
return _usrp1.usrp1_sink_base_set_interp_rate(*args)
def set_nchannels(*args):
"""set_nchannels(self, int nchan) -> bool"""
return _usrp1.usrp1_sink_base_set_nchannels(*args)
def set_mux(*args):
"""set_mux(self, int mux) -> bool"""
print "set_mux", args
return _usrp1.usrp1_sink_base_set_mux(*args)
def set_tx_freq(*args):
"""set_tx_freq(self, int channel, double freq) -> bool"""
print "set_tx_freq", args
return _usrp1.usrp1_sink_base_set_tx_freq(*args)
def set_verbose(*args):
"""set_verbose(self, bool verbose)"""
print "set_verbose", args
return _usrp1.usrp1_sink_base_set_verbose(*args)
def fpga_master_clock_freq(*args):
"""fpga_master_clock_freq(self) -> long"""
return _usrp1.usrp1_sink_base_fpga_master_clock_freq(*args)
def converter_rate(*args):
"""converter_rate(self) -> long"""
return _usrp1.usrp1_sink_base_converter_rate(*args)
def dac_rate(*args):
"""dac_rate(self) -> long"""
return _usrp1.usrp1_sink_base_dac_rate(*args)
def dac_freq(*args):
"""dac_freq(self) -> long"""
return _usrp1.usrp1_sink_base_dac_freq(*args)
def interp_rate(*args):
"""interp_rate(self) -> unsigned int"""
return _usrp1.usrp1_sink_base_interp_rate(*args)
def tx_freq(*args):
"""tx_freq(self, int channel) -> double"""
return _usrp1.usrp1_sink_base_tx_freq(*args)
def nunderruns(*args):
"""nunderruns(self) -> int"""
return _usrp1.usrp1_sink_base_nunderruns(*args)
def set_pga(*args):
"""set_pga(self, int which, double gain_in_db) -> bool"""
print "set_pga", args
return _usrp1.usrp1_sink_base_set_pga(*args)
def pga(*args):
"""pga(self, int which) -> double"""
return _usrp1.usrp1_sink_base_pga(*args)
def pga_min(*args):
"""pga_min(self) -> double"""
return _usrp1.usrp1_sink_base_pga_min(*args)
def pga_max(*args):
"""pga_max(self) -> double"""
return _usrp1.usrp1_sink_base_pga_max(*args)
def pga_db_per_step(*args):
"""pga_db_per_step(self) -> double"""
return _usrp1.usrp1_sink_base_pga_db_per_step(*args)
def daughterboard_id(*args):
"""daughterboard_id(self, int which_dboard) -> int"""
return _usrp1.usrp1_sink_base_daughterboard_id(*args)
def set_adc_offset(*args):
"""set_adc_offset(self, int which, int offset) -> bool"""
print "set_adc_offset", args
return _usrp1.usrp1_sink_base_set_adc_offset(*args)
def set_dac_offset(*args):
"""set_dac_offset(self, int which, int offset, int offset_pin) ->
bool"""
print "set_dac_offset", args
return _usrp1.usrp1_sink_base_set_dac_offset(*args)
def set_adc_buffer_bypass(*args):
"""set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
print "set_adc_buffer_bypass", args
return _usrp1.usrp1_sink_base_set_adc_buffer_bypass(*args)
def serial_number(*args):
"""serial_number(self) -> string"""
return _usrp1.usrp1_sink_base_serial_number(*args)
def _write_oe(*args):
"""_write_oe(self, int which_dboard, int value, int mask) -> bool"""
print "_write_oe",args
return _usrp1.usrp1_sink_base__write_oe(*args)
def write_io(*args):
"""write_io(self, int which_dboard, int value, int mask) -> bool"""
print "_write_io",args
return _usrp1.usrp1_sink_base_write_io(*args)
def read_io(*args):
"""read_io(self, int which_dboard) -> int"""
return _usrp1.usrp1_sink_base_read_io(*args)
def write_aux_dac(*args):
"""write_aux_dac(self, int which_dboard, int which_dac, int value) ->
bool"""
print "write_aux_dac",args
return _usrp1.usrp1_sink_base_write_aux_dac(*args)
def read_aux_adc(*args):
"""read_aux_adc(self, int which_dboard, int which_adc) -> int"""
return _usrp1.usrp1_sink_base_read_aux_adc(*args)
def write_eeprom(*args):
"""write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) ->
bool"""
print "write_eeprom",args
return _usrp1.usrp1_sink_base_write_eeprom(*args)
def read_eeprom(*args):
"""read_eeprom(self, int i2c_addr, int eeprom_offset, int len) ->
string"""
return _usrp1.usrp1_sink_base_read_eeprom(*args)
def write_i2c(*args):
"""write_i2c(self, int i2c_addr, string buf) -> bool"""
print "write_i2c",args
return _usrp1.usrp1_sink_base_write_i2c(*args)
def read_i2c(*args):
"""read_i2c(self, int i2c_addr, int len) -> string"""
return _usrp1.usrp1_sink_base_read_i2c(*args)
def _write_fpga_reg(*args):
"""_write_fpga_reg(self, int regno, int value) -> bool"""
print "_write_fpga_reg",args
return _usrp1.usrp1_sink_base__write_fpga_reg(*args)
def _read_fpga_reg(*args):
"""_read_fpga_reg(self, int regno) -> int"""
return _usrp1.usrp1_sink_base__read_fpga_reg(*args)
def _write_9862(*args):
"""_write_9862(self, int which_codec, int regno, unsigned char value)
-> bool"""
print "_write_9862",args
return _usrp1.usrp1_sink_base__write_9862(*args)
def _read_9862(*args):
"""_read_9862(self, int which_codec, int regno) -> int"""
return _usrp1.usrp1_sink_base__read_9862(*args)
def _write_spi(*args):
"""_write_spi(self, int optional_header, int enables, int format,
string buf) -> bool"""
print "_write_spi",args
return _usrp1.usrp1_sink_base__write_spi(*args)
def _read_spi(*args):
"""_read_spi(self, int optional_header, int enables, int format, int
len) -> string"""
return _usrp1.usrp1_sink_base__read_spi(*args)
usrp1_sink_base_swigregister = _usrp1.usrp1_sink_base_swigregister
usrp1_sink_base_swigregister(usrp1_sink_base)
class usrp1_source_base(object):
"""Proxy of C++ usrp1_source_base class"""
thisown = _swig_property(lambda x: x.this.own(), lambda x, v:
x.this.own(v), doc='The membership flag')
def __init__(self): raise AttributeError, "No constructor defined"
__repr__ = _swig_repr
__swig_destroy__ = _usrp1.delete_usrp1_source_base
__del__ = lambda self : None;
def set_decim_rate(*args):
"""set_decim_rate(self, unsigned int rate) -> bool"""
print "set_decim_rate", args
return _usrp1.usrp1_source_base_set_decim_rate(*args)
def set_nchannels(*args):
"""set_nchannels(self, int nchan) -> bool"""
print "set_nchannels", args
return _usrp1.usrp1_source_base_set_nchannels(*args)
def set_mux(*args):
"""set_mux(self, int mux) -> bool"""
print "set_mux", args
return _usrp1.usrp1_source_base_set_mux(*args)
def set_rx_freq(*args):
"""set_rx_freq(self, int channel, double freq) -> bool"""
print "set_rx_freq", args
return _usrp1.usrp1_source_base_set_rx_freq(*args)
def set_fpga_mode(*args):
"""set_fpga_mode(self, int mode) -> bool"""
print "set_fpga_mode", args
return _usrp1.usrp1_source_base_set_fpga_mode(*args)
def set_ddc_phase(*args):
"""set_ddc_phase(self, int channel, int phase) -> bool"""
print "set_ddc_phase", args
return _usrp1.usrp1_source_base_set_ddc_phase(*args)
def set_verbose(*args):
"""set_verbose(self, bool verbose)"""
print "set_verbose", args
return _usrp1.usrp1_source_base_set_verbose(*args)
def fpga_master_clock_freq(*args):
"""fpga_master_clock_freq(self) -> long"""
return _usrp1.usrp1_source_base_fpga_master_clock_freq(*args)
def converter_rate(*args):
"""converter_rate(self) -> long"""
return _usrp1.usrp1_source_base_converter_rate(*args)
def adc_rate(*args):
"""adc_rate(self) -> long"""
return _usrp1.usrp1_source_base_adc_rate(*args)
def adc_freq(*args):
"""adc_freq(self) -> long"""
return _usrp1.usrp1_source_base_adc_freq(*args)
def decim_rate(*args):
"""decim_rate(self) -> unsigned int"""
return _usrp1.usrp1_source_base_decim_rate(*args)
def rx_freq(*args):
"""rx_freq(self, int channel) -> double"""
return _usrp1.usrp1_source_base_rx_freq(*args)
def noverruns(*args):
"""noverruns(self) -> int"""
return _usrp1.usrp1_source_base_noverruns(*args)
def set_pga(*args):
"""set_pga(self, int which, double gain_in_db) -> bool"""
print "set_pga", args
return _usrp1.usrp1_source_base_set_pga(*args)
def pga(*args):
"""pga(self, int which) -> double"""
return _usrp1.usrp1_source_base_pga(*args)
def pga_min(*args):
"""pga_min(self) -> double"""
return _usrp1.usrp1_source_base_pga_min(*args)
def pga_max(*args):
"""pga_max(self) -> double"""
return _usrp1.usrp1_source_base_pga_max(*args)
def pga_db_per_step(*args):
"""pga_db_per_step(self) -> double"""
return _usrp1.usrp1_source_base_pga_db_per_step(*args)
def daughterboard_id(*args):
"""daughterboard_id(self, int which_dboard) -> int"""
return _usrp1.usrp1_source_base_daughterboard_id(*args)
def set_adc_offset(*args):
"""set_adc_offset(self, int which, int offset) -> bool"""
print "set_adc_offset", args
return _usrp1.usrp1_source_base_set_adc_offset(*args)
def set_dac_offset(*args):
"""set_dac_offset(self, int which, int offset, int offset_pin) ->
bool"""
print "set_dac_offset", args
return _usrp1.usrp1_source_base_set_dac_offset(*args)
def set_adc_buffer_bypass(*args):
"""set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
print "set_adc_buffer_bypass", args
return _usrp1.usrp1_source_base_set_adc_buffer_bypass(*args)
def serial_number(*args):
"""serial_number(self) -> string"""
return _usrp1.usrp1_source_base_serial_number(*args)
def _write_oe(*args):
"""_write_oe(self, int which_dboard, int value, int mask) -> bool"""
print "_write_oe",args
return _usrp1.usrp1_source_base__write_oe(*args)
def write_io(*args):
"""write_io(self, int which_dboard, int value, int mask) -> bool"""
print "_write_io",args
return _usrp1.usrp1_source_base_write_io(*args)
def read_io(*args):
"""read_io(self, int which_dboard) -> int"""
return _usrp1.usrp1_source_base_read_io(*args)
def set_dc_offset_cl_enable(*args):
"""set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
print "set_dc_offset_cl_enable", args
return _usrp1.usrp1_source_base_set_dc_offset_cl_enable(*args)
def set_format(*args):
"""set_format(self, unsigned int format) -> bool"""
print "set_format", args
return _usrp1.usrp1_source_base_set_format(*args)
def format(*args):
"""format(self) -> unsigned int"""
return _usrp1.usrp1_source_base_format(*args)
def make_format(*args):
"""
make_format(int width=16, int shift=0, bool want_q=True, bool
bypass_halfband=False) -> unsigned int
make_format(int width=16, int shift=0, bool want_q=True) -> unsigned int
make_format(int width=16, int shift=0) -> unsigned int
make_format(int width=16) -> unsigned int
make_format() -> unsigned int
"""
return _usrp1.usrp1_source_base_make_format(*args)
make_format = staticmethod(make_format)
def format_width(*args):
"""format_width(unsigned int format) -> int"""
return _usrp1.usrp1_source_base_format_width(*args)
format_width = staticmethod(format_width)
def format_shift(*args):
"""format_shift(unsigned int format) -> int"""
return _usrp1.usrp1_source_base_format_shift(*args)
format_shift = staticmethod(format_shift)
def format_want_q(*args):
"""format_want_q(unsigned int format) -> bool"""
return _usrp1.usrp1_source_base_format_want_q(*args)
format_want_q = staticmethod(format_want_q)
def format_bypass_halfband(*args):
"""format_bypass_halfband(unsigned int format) -> bool"""
return _usrp1.usrp1_source_base_format_bypass_halfband(*args)
format_bypass_halfband = staticmethod(format_bypass_halfband)
def write_aux_dac(*args):
"""write_aux_dac(self, int which_dboard, int which_dac, int value) ->
bool"""
print "write_aux_dac",args
return _usrp1.usrp1_source_base_write_aux_dac(*args)
def read_aux_adc(*args):
"""read_aux_adc(self, int which_dboard, int which_adc) -> int"""
return _usrp1.usrp1_source_base_read_aux_adc(*args)
def write_eeprom(*args):
"""write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) ->
bool"""
print "write_eeprom",args
return _usrp1.usrp1_source_base_write_eeprom(*args)
def read_eeprom(*args):
"""read_eeprom(self, int i2c_addr, int eeprom_offset, int len) ->
string"""
return _usrp1.usrp1_source_base_read_eeprom(*args)
def write_i2c(*args):
"""write_i2c(self, int i2c_addr, string buf) -> bool"""
print "write_i2c",args
return _usrp1.usrp1_source_base_write_i2c(*args)
def read_i2c(*args):
"""read_i2c(self, int i2c_addr, int len) -> string"""
return _usrp1.usrp1_source_base_read_i2c(*args)
def _write_fpga_reg(*args):
"""_write_fpga_reg(self, int regno, int value) -> bool"""
print "_write_fpga_reg",args
return _usrp1.usrp1_source_base__write_fpga_reg(*args)
def _write_fpga_reg_masked(*args):
"""_write_fpga_reg_masked(self, int regno, int value, int mask) ->
bool"""
print "_write_fpga_reg_masked",args
return _usrp1.usrp1_source_base__write_fpga_reg_masked(*args)
def _read_fpga_reg(*args):
"""_read_fpga_reg(self, int regno) -> int"""
return _usrp1.usrp1_source_base__read_fpga_reg(*args)
def _write_9862(*args):
"""_write_9862(self, int which_codec, int regno, unsigned char value)
-> bool"""
print "_write_9862",args
return _usrp1.usrp1_source_base__write_9862(*args)
def _read_9862(*args):
"""_read_9862(self, int which_codec, int regno) -> int"""
return _usrp1.usrp1_source_base__read_9862(*args)
def _write_spi(*args):
"""_write_spi(self, int optional_header, int enables, int format,
string buf) -> bool"""
print "_write_spi",args
return _usrp1.usrp1_source_base__write_spi(*args)
def _read_spi(*args):
"""_read_spi(self, int optional_header, int enables, int format, int
len) -> string"""
return _usrp1.usrp1_source_base__read_spi(*args)
usrp1_source_base_swigregister = _usrp1.usrp1_source_base_swigregister
usrp1_source_base_swigregister(usrp1_source_base)
def usrp1_source_base_make_format(*args):
"""
make_format(int width=16, int shift=0, bool want_q=True, bool
bypass_halfband=False) -> unsigned int
make_format(int width=16, int shift=0, bool want_q=True) -> unsigned int
make_format(int width=16, int shift=0) -> unsigned int
make_format(int width=16) -> unsigned int
usrp1_source_base_make_format() -> unsigned int
"""
return _usrp1.usrp1_source_base_make_format(*args)
def usrp1_source_base_format_width(*args):
"""usrp1_source_base_format_width(unsigned int format) -> int"""
return _usrp1.usrp1_source_base_format_width(*args)
def usrp1_source_base_format_shift(*args):
"""usrp1_source_base_format_shift(unsigned int format) -> int"""
return _usrp1.usrp1_source_base_format_shift(*args)
def usrp1_source_base_format_want_q(*args):
"""usrp1_source_base_format_want_q(unsigned int format) -> bool"""
return _usrp1.usrp1_source_base_format_want_q(*args)
def usrp1_source_base_format_bypass_halfband(*args):
"""usrp1_source_base_format_bypass_halfband(unsigned int format) -> bool"""
return _usrp1.usrp1_source_base_format_bypass_halfband(*args)
class usrp1_sink_c_sptr(object):
"""Proxy of C++ usrp1_sink_c_sptr class"""
thisown = _swig_property(lambda x: x.this.own(), lambda x, v:
x.this.own(v), doc='The membership flag')
__repr__ = _swig_repr
def __init__(self, *args):
"""
__init__(self) -> usrp1_sink_c_sptr
__init__(self, p) -> usrp1_sink_c_sptr
"""
this = _usrp1.new_usrp1_sink_c_sptr(*args)
try: self.this.append(this)
except: self.this = this
def __deref__(*args):
"""__deref__(self)"""
return _usrp1.usrp1_sink_c_sptr___deref__(*args)
__swig_destroy__ = _usrp1.delete_usrp1_sink_c_sptr
__del__ = lambda self : None;
def set_interp_rate(*args):
"""set_interp_rate(self, unsigned int rate) -> bool"""
print "set_interp_rate", args
return _usrp1.usrp1_sink_c_sptr_set_interp_rate(*args)
def set_nchannels(*args):
"""set_nchannels(self, int nchan) -> bool"""
print "set_nchannels", args
return _usrp1.usrp1_sink_c_sptr_set_nchannels(*args)
def set_mux(*args):
"""set_mux(self, int mux) -> bool"""
print "set_mux", args
return _usrp1.usrp1_sink_c_sptr_set_mux(*args)
def set_tx_freq(*args):
"""set_tx_freq(self, int channel, double freq) -> bool"""
print "set_tx_freq", args
return _usrp1.usrp1_sink_c_sptr_set_tx_freq(*args)
def set_verbose(*args):
"""set_verbose(self, bool verbose)"""
print "set_verbose", args
return _usrp1.usrp1_sink_c_sptr_set_verbose(*args)
def fpga_master_clock_freq(*args):
"""fpga_master_clock_freq(self) -> long"""
return _usrp1.usrp1_sink_c_sptr_fpga_master_clock_freq(*args)
def converter_rate(*args):
"""converter_rate(self) -> long"""
return _usrp1.usrp1_sink_c_sptr_converter_rate(*args)
def dac_rate(*args):
"""dac_rate(self) -> long"""
return _usrp1.usrp1_sink_c_sptr_dac_rate(*args)
def dac_freq(*args):
"""dac_freq(self) -> long"""
return _usrp1.usrp1_sink_c_sptr_dac_freq(*args)
def interp_rate(*args):
"""interp_rate(self) -> unsigned int"""
return _usrp1.usrp1_sink_c_sptr_interp_rate(*args)
def tx_freq(*args):
"""tx_freq(self, int channel) -> double"""
return _usrp1.usrp1_sink_c_sptr_tx_freq(*args)
def nunderruns(*args):
"""nunderruns(self) -> int"""
return _usrp1.usrp1_sink_c_sptr_nunderruns(*args)
def set_pga(*args):
"""set_pga(self, int which, double gain_in_db) -> bool"""
print "set_pga", args
return _usrp1.usrp1_sink_c_sptr_set_pga(*args)
def pga(*args):
"""pga(self, int which) -> double"""
return _usrp1.usrp1_sink_c_sptr_pga(*args)
def pga_min(*args):
"""pga_min(self) -> double"""
return _usrp1.usrp1_sink_c_sptr_pga_min(*args)
def pga_max(*args):
"""pga_max(self) -> double"""
return _usrp1.usrp1_sink_c_sptr_pga_max(*args)
def pga_db_per_step(*args):
"""pga_db_per_step(self) -> double"""
return _usrp1.usrp1_sink_c_sptr_pga_db_per_step(*args)
def daughterboard_id(*args):
"""daughterboard_id(self, int which_dboard) -> int"""
return _usrp1.usrp1_sink_c_sptr_daughterboard_id(*args)
def set_adc_offset(*args):
"""set_adc_offset(self, int which, int offset) -> bool"""
print "set_adc_offset", args
return _usrp1.usrp1_sink_c_sptr_set_adc_offset(*args)
def set_dac_offset(*args):
"""set_dac_offset(self, int which, int offset, int offset_pin) ->
bool"""
print "set_dac_offset", args
return _usrp1.usrp1_sink_c_sptr_set_dac_offset(*args)
def set_adc_buffer_bypass(*args):
"""set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
print "set_adc_buffer_bypass", args
return _usrp1.usrp1_sink_c_sptr_set_adc_buffer_bypass(*args)
def serial_number(*args):
"""serial_number(self) -> string"""
return _usrp1.usrp1_sink_c_sptr_serial_number(*args)
def _write_oe(*args):
"""_write_oe(self, int which_dboard, int value, int mask) -> bool"""
print "_write_oe",args
return _usrp1.usrp1_sink_c_sptr__write_oe(*args)
def write_io(*args):
"""write_io(self, int which_dboard, int value, int mask) -> bool"""
print "_write_io",args
return _usrp1.usrp1_sink_c_sptr_write_io(*args)
def read_io(*args):
"""read_io(self, int which_dboard) -> int"""
return _usrp1.usrp1_sink_c_sptr_read_io(*args)
def write_aux_dac(*args):
"""write_aux_dac(self, int which_dboard, int which_dac, int value) ->
bool"""
print "write_aux_dac",args
return _usrp1.usrp1_sink_c_sptr_write_aux_dac(*args)
def read_aux_adc(*args):
"""read_aux_adc(self, int which_dboard, int which_adc) -> int"""
return _usrp1.usrp1_sink_c_sptr_read_aux_adc(*args)
def write_eeprom(*args):
"""write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) ->
bool"""
print "write_eeprom",args
return _usrp1.usrp1_sink_c_sptr_write_eeprom(*args)
def read_eeprom(*args):
"""read_eeprom(self, int i2c_addr, int eeprom_offset, int len) ->
string"""
return _usrp1.usrp1_sink_c_sptr_read_eeprom(*args)
def write_i2c(*args):
"""write_i2c(self, int i2c_addr, string buf) -> bool"""
print "write_i2c",args
return _usrp1.usrp1_sink_c_sptr_write_i2c(*args)
def read_i2c(*args):
"""read_i2c(self, int i2c_addr, int len) -> string"""
return _usrp1.usrp1_sink_c_sptr_read_i2c(*args)
def _write_fpga_reg(*args):
"""_write_fpga_reg(self, int regno, int value) -> bool"""
print "_write_fpga_reg",args
return _usrp1.usrp1_sink_c_sptr__write_fpga_reg(*args)
def _read_fpga_reg(*args):
"""_read_fpga_reg(self, int regno) -> int"""
return _usrp1.usrp1_sink_c_sptr__read_fpga_reg(*args)
def _write_9862(*args):
"""_write_9862(self, int which_codec, int regno, unsigned char value)
-> bool"""
print "_write_9862",args
return _usrp1.usrp1_sink_c_sptr__write_9862(*args)
def _read_9862(*args):
"""_read_9862(self, int which_codec, int regno) -> int"""
return _usrp1.usrp1_sink_c_sptr__read_9862(*args)
def _write_spi(*args):
"""_write_spi(self, int optional_header, int enables, int format,
string buf) -> bool"""
print "_write_spi",args
return _usrp1.usrp1_sink_c_sptr__write_spi(*args)
def _read_spi(*args):
"""_read_spi(self, int optional_header, int enables, int format, int
len) -> string"""
return _usrp1.usrp1_sink_c_sptr__read_spi(*args)
def history(*args):
"""history(self) -> unsigned int"""
return _usrp1.usrp1_sink_c_sptr_history(*args)
def output_multiple(*args):
"""output_multiple(self) -> int"""
return _usrp1.usrp1_sink_c_sptr_output_multiple(*args)
def relative_rate(*args):
"""relative_rate(self) -> double"""
return _usrp1.usrp1_sink_c_sptr_relative_rate(*args)
def start(*args):
"""start(self) -> bool"""
return _usrp1.usrp1_sink_c_sptr_start(*args)
def stop(*args):
"""stop(self) -> bool"""
return _usrp1.usrp1_sink_c_sptr_stop(*args)
def detail(*args):
"""detail(self) -> gr_block_detail_sptr"""
return _usrp1.usrp1_sink_c_sptr_detail(*args)
def set_detail(*args):
"""set_detail(self, gr_block_detail_sptr detail)"""
print "set_detail", args
return _usrp1.usrp1_sink_c_sptr_set_detail(*args)
def name(*args):
"""name(self) -> string"""
return _usrp1.usrp1_sink_c_sptr_name(*args)
def input_signature(*args):
"""input_signature(self) -> gr_io_signature_sptr"""
return _usrp1.usrp1_sink_c_sptr_input_signature(*args)
def output_signature(*args):
"""output_signature(self) -> gr_io_signature_sptr"""
return _usrp1.usrp1_sink_c_sptr_output_signature(*args)
def unique_id(*args):
"""unique_id(self) -> long"""
return _usrp1.usrp1_sink_c_sptr_unique_id(*args)
def basic_block(*args):
"""basic_block(self) -> gr_basic_block_sptr"""
return _usrp1.usrp1_sink_c_sptr_basic_block(*args)
def check_topology(*args):
"""check_topology(self, int ninputs, int noutputs) -> bool"""
return _usrp1.usrp1_sink_c_sptr_check_topology(*args)
usrp1_sink_c_sptr_swigregister = _usrp1.usrp1_sink_c_sptr_swigregister
usrp1_sink_c_sptr_swigregister(usrp1_sink_c_sptr)
def usrp1_sink_c_block(*args):
"""usrp1_sink_c_block(usrp1_sink_c_sptr r) -> gr_block_sptr"""
return _usrp1.usrp1_sink_c_block(*args)
usrp1_sink_c_sptr.block = lambda self: usrp1_sink_c_block (self)
usrp1_sink_c_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(),
self.unique_id ())
def sink_c(*args):
"""
sink_c(int which_board, unsigned int interp_rate, int nchan,
int mux, int fusb_block_size, int fusb_nblocks,
string fpga_filename, string firmware_filename) -> usrp1_sink_c_sptr
"""
return _usrp1.sink_c(*args)
class usrp1_sink_s_sptr(object):
"""Proxy of C++ usrp1_sink_s_sptr class"""
thisown = _swig_property(lambda x: x.this.own(), lambda x, v:
x.this.own(v), doc='The membership flag')
__repr__ = _swig_repr
def __init__(self, *args):
"""
__init__(self) -> usrp1_sink_s_sptr
__init__(self, p) -> usrp1_sink_s_sptr
"""
this = _usrp1.new_usrp1_sink_s_sptr(*args)
try: self.this.append(this)
except: self.this = this
def __deref__(*args):
"""__deref__(self)"""
return _usrp1.usrp1_sink_s_sptr___deref__(*args)
__swig_destroy__ = _usrp1.delete_usrp1_sink_s_sptr
__del__ = lambda self : None;
def set_interp_rate(*args):
"""set_interp_rate(self, unsigned int rate) -> bool"""
print "set_interp_rate", args
return _usrp1.usrp1_sink_s_sptr_set_interp_rate(*args)
def set_nchannels(*args):
"""set_nchannels(self, int nchan) -> bool"""
print "set_nchannels", args
return _usrp1.usrp1_sink_s_sptr_set_nchannels(*args)
def set_mux(*args):
"""set_mux(self, int mux) -> bool"""
print "set_mux", args
return _usrp1.usrp1_sink_s_sptr_set_mux(*args)
def set_tx_freq(*args):
"""set_tx_freq(self, int channel, double freq) -> bool"""
print "set_tx_freq", args
return _usrp1.usrp1_sink_s_sptr_set_tx_freq(*args)
def set_verbose(*args):
"""set_verbose(self, bool verbose)"""
print "set_verbose", args
return _usrp1.usrp1_sink_s_sptr_set_verbose(*args)
def fpga_master_clock_freq(*args):
"""fpga_master_clock_freq(self) -> long"""
return _usrp1.usrp1_sink_s_sptr_fpga_master_clock_freq(*args)
def converter_rate(*args):
"""converter_rate(self) -> long"""
return _usrp1.usrp1_sink_s_sptr_converter_rate(*args)
def dac_rate(*args):
"""dac_rate(self) -> long"""
return _usrp1.usrp1_sink_s_sptr_dac_rate(*args)
def dac_freq(*args):
"""dac_freq(self) -> long"""
return _usrp1.usrp1_sink_s_sptr_dac_freq(*args)
def interp_rate(*args):
"""interp_rate(self) -> unsigned int"""
return _usrp1.usrp1_sink_s_sptr_interp_rate(*args)
def tx_freq(*args):
"""tx_freq(self, int channel) -> double"""
return _usrp1.usrp1_sink_s_sptr_tx_freq(*args)
def nunderruns(*args):
"""nunderruns(self) -> int"""
return _usrp1.usrp1_sink_s_sptr_nunderruns(*args)
def set_pga(*args):
"""set_pga(self, int which, double gain_in_db) -> bool"""
print "set_pga", args
return _usrp1.usrp1_sink_s_sptr_set_pga(*args)
def pga(*args):
"""pga(self, int which) -> double"""
return _usrp1.usrp1_sink_s_sptr_pga(*args)
def pga_min(*args):
"""pga_min(self) -> double"""
return _usrp1.usrp1_sink_s_sptr_pga_min(*args)
def pga_max(*args):
"""pga_max(self) -> double"""
return _usrp1.usrp1_sink_s_sptr_pga_max(*args)
def pga_db_per_step(*args):
"""pga_db_per_step(self) -> double"""
return _usrp1.usrp1_sink_s_sptr_pga_db_per_step(*args)
def daughterboard_id(*args):
"""daughterboard_id(self, int which_dboard) -> int"""
return _usrp1.usrp1_sink_s_sptr_daughterboard_id(*args)
def set_adc_offset(*args):
"""set_adc_offset(self, int which, int offset) -> bool"""
print "set_adc_offset", args
return _usrp1.usrp1_sink_s_sptr_set_adc_offset(*args)
def set_dac_offset(*args):
"""set_dac_offset(self, int which, int offset, int offset_pin) ->
bool"""
print "set_dac_offset", args
return _usrp1.usrp1_sink_s_sptr_set_dac_offset(*args)
def set_adc_buffer_bypass(*args):
"""set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
print "set_adc_buffer_bypass", args
return _usrp1.usrp1_sink_s_sptr_set_adc_buffer_bypass(*args)
def serial_number(*args):
"""serial_number(self) -> string"""
return _usrp1.usrp1_sink_s_sptr_serial_number(*args)
def _write_oe(*args):
"""_write_oe(self, int which_dboard, int value, int mask) -> bool"""
print "_write_oe",args
return _usrp1.usrp1_sink_s_sptr__write_oe(*args)
def write_io(*args):
"""write_io(self, int which_dboard, int value, int mask) -> bool"""
print "_write_io",args
return _usrp1.usrp1_sink_s_sptr_write_io(*args)
def read_io(*args):
"""read_io(self, int which_dboard) -> int"""
return _usrp1.usrp1_sink_s_sptr_read_io(*args)
def write_aux_dac(*args):
"""write_aux_dac(self, int which_dboard, int which_dac, int value) ->
bool"""
print "write_aux_dac",args
return _usrp1.usrp1_sink_s_sptr_write_aux_dac(*args)
def read_aux_adc(*args):
"""read_aux_adc(self, int which_dboard, int which_adc) -> int"""
return _usrp1.usrp1_sink_s_sptr_read_aux_adc(*args)
def write_eeprom(*args):
"""write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) ->
bool"""
print "write_eeprom",args
return _usrp1.usrp1_sink_s_sptr_write_eeprom(*args)
def read_eeprom(*args):
"""read_eeprom(self, int i2c_addr, int eeprom_offset, int len) ->
string"""
return _usrp1.usrp1_sink_s_sptr_read_eeprom(*args)
def write_i2c(*args):
"""write_i2c(self, int i2c_addr, string buf) -> bool"""
print "write_i2c",args
return _usrp1.usrp1_sink_s_sptr_write_i2c(*args)
def read_i2c(*args):
"""read_i2c(self, int i2c_addr, int len) -> string"""
return _usrp1.usrp1_sink_s_sptr_read_i2c(*args)
def _write_fpga_reg(*args):
"""_write_fpga_reg(self, int regno, int value) -> bool"""
print "_write_fpga_reg",args
return _usrp1.usrp1_sink_s_sptr__write_fpga_reg(*args)
def _read_fpga_reg(*args):
"""_read_fpga_reg(self, int regno) -> int"""
return _usrp1.usrp1_sink_s_sptr__read_fpga_reg(*args)
def _write_9862(*args):
"""_write_9862(self, int which_codec, int regno, unsigned char value)
-> bool"""
print "_write_9862",args
return _usrp1.usrp1_sink_s_sptr__write_9862(*args)
def _read_9862(*args):
"""_read_9862(self, int which_codec, int regno) -> int"""
return _usrp1.usrp1_sink_s_sptr__read_9862(*args)
def _write_spi(*args):
"""_write_spi(self, int optional_header, int enables, int format,
string buf) -> bool"""
print "_write_spi",args
return _usrp1.usrp1_sink_s_sptr__write_spi(*args)
def _read_spi(*args):
"""_read_spi(self, int optional_header, int enables, int format, int
len) -> string"""
return _usrp1.usrp1_sink_s_sptr__read_spi(*args)
def history(*args):
"""history(self) -> unsigned int"""
return _usrp1.usrp1_sink_s_sptr_history(*args)
def output_multiple(*args):
"""output_multiple(self) -> int"""
return _usrp1.usrp1_sink_s_sptr_output_multiple(*args)
def relative_rate(*args):
"""relative_rate(self) -> double"""
return _usrp1.usrp1_sink_s_sptr_relative_rate(*args)
def start(*args):
"""start(self) -> bool"""
return _usrp1.usrp1_sink_s_sptr_start(*args)
def stop(*args):
"""stop(self) -> bool"""
return _usrp1.usrp1_sink_s_sptr_stop(*args)
def detail(*args):
"""detail(self) -> gr_block_detail_sptr"""
return _usrp1.usrp1_sink_s_sptr_detail(*args)
def set_detail(*args):
"""set_detail(self, gr_block_detail_sptr detail)"""
print "set_detail", args
return _usrp1.usrp1_sink_s_sptr_set_detail(*args)
def name(*args):
"""name(self) -> string"""
return _usrp1.usrp1_sink_s_sptr_name(*args)
def input_signature(*args):
"""input_signature(self) -> gr_io_signature_sptr"""
return _usrp1.usrp1_sink_s_sptr_input_signature(*args)
def output_signature(*args):
"""output_signature(self) -> gr_io_signature_sptr"""
return _usrp1.usrp1_sink_s_sptr_output_signature(*args)
def unique_id(*args):
"""unique_id(self) -> long"""
return _usrp1.usrp1_sink_s_sptr_unique_id(*args)
def basic_block(*args):
"""basic_block(self) -> gr_basic_block_sptr"""
return _usrp1.usrp1_sink_s_sptr_basic_block(*args)
def check_topology(*args):
"""check_topology(self, int ninputs, int noutputs) -> bool"""
return _usrp1.usrp1_sink_s_sptr_check_topology(*args)
usrp1_sink_s_sptr_swigregister = _usrp1.usrp1_sink_s_sptr_swigregister
usrp1_sink_s_sptr_swigregister(usrp1_sink_s_sptr)
def usrp1_sink_s_block(*args):
"""usrp1_sink_s_block(usrp1_sink_s_sptr r) -> gr_block_sptr"""
return _usrp1.usrp1_sink_s_block(*args)
usrp1_sink_s_sptr.block = lambda self: usrp1_sink_s_block (self)
usrp1_sink_s_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" % (self.name(),
self.unique_id ())
def sink_s(*args):
"""
sink_s(int which_board, unsigned int interp_rate, int nchan,
int mux, int fusb_block_size, int fusb_nblocks,
string fpga_filename, string firmware_filename) -> usrp1_sink_s_sptr
"""
return _usrp1.sink_s(*args)
class usrp1_source_c_sptr(object):
"""Proxy of C++ usrp1_source_c_sptr class"""
thisown = _swig_property(lambda x: x.this.own(), lambda x, v:
x.this.own(v), doc='The membership flag')
__repr__ = _swig_repr
def __init__(self, *args):
"""
__init__(self) -> usrp1_source_c_sptr
__init__(self, p) -> usrp1_source_c_sptr
"""
this = _usrp1.new_usrp1_source_c_sptr(*args)
try: self.this.append(this)
except: self.this = this
def __deref__(*args):
"""__deref__(self)"""
return _usrp1.usrp1_source_c_sptr___deref__(*args)
__swig_destroy__ = _usrp1.delete_usrp1_source_c_sptr
__del__ = lambda self : None;
def set_decim_rate(*args):
"""set_decim_rate(self, unsigned int rate) -> bool"""
print "set_decim_rate", args
return _usrp1.usrp1_source_c_sptr_set_decim_rate(*args)
def set_nchannels(*args):
"""set_nchannels(self, int nchan) -> bool"""
print "set_nchannels", args
return _usrp1.usrp1_source_c_sptr_set_nchannels(*args)
def set_mux(*args):
"""set_mux(self, int mux) -> bool"""
print "set_mux", args
return _usrp1.usrp1_source_c_sptr_set_mux(*args)
def set_rx_freq(*args):
"""set_rx_freq(self, int channel, double freq) -> bool"""
print "set_rx_freq", args
return _usrp1.usrp1_source_c_sptr_set_rx_freq(*args)
def set_fpga_mode(*args):
"""set_fpga_mode(self, int mode) -> bool"""
print "set_fpga_mode", args
return _usrp1.usrp1_source_c_sptr_set_fpga_mode(*args)
def set_ddc_phase(*args):
"""set_ddc_phase(self, int channel, int phase) -> bool"""
print "set_ddc_phase", args
return _usrp1.usrp1_source_c_sptr_set_ddc_phase(*args)
def set_verbose(*args):
"""set_verbose(self, bool verbose)"""
print "set_verbose", args
return _usrp1.usrp1_source_c_sptr_set_verbose(*args)
def fpga_master_clock_freq(*args):
"""fpga_master_clock_freq(self) -> long"""
return _usrp1.usrp1_source_c_sptr_fpga_master_clock_freq(*args)
def converter_rate(*args):
"""converter_rate(self) -> long"""
return _usrp1.usrp1_source_c_sptr_converter_rate(*args)
def adc_rate(*args):
"""adc_rate(self) -> long"""
return _usrp1.usrp1_source_c_sptr_adc_rate(*args)
def adc_freq(*args):
"""adc_freq(self) -> long"""
return _usrp1.usrp1_source_c_sptr_adc_freq(*args)
def decim_rate(*args):
"""decim_rate(self) -> unsigned int"""
return _usrp1.usrp1_source_c_sptr_decim_rate(*args)
def rx_freq(*args):
"""rx_freq(self, int channel) -> double"""
return _usrp1.usrp1_source_c_sptr_rx_freq(*args)
def noverruns(*args):
"""noverruns(self) -> int"""
return _usrp1.usrp1_source_c_sptr_noverruns(*args)
def set_pga(*args):
"""set_pga(self, int which, double gain_in_db) -> bool"""
print "set_pga", args
return _usrp1.usrp1_source_c_sptr_set_pga(*args)
def pga(*args):
"""pga(self, int which) -> double"""
return _usrp1.usrp1_source_c_sptr_pga(*args)
def pga_min(*args):
"""pga_min(self) -> double"""
return _usrp1.usrp1_source_c_sptr_pga_min(*args)
def pga_max(*args):
"""pga_max(self) -> double"""
return _usrp1.usrp1_source_c_sptr_pga_max(*args)
def pga_db_per_step(*args):
"""pga_db_per_step(self) -> double"""
return _usrp1.usrp1_source_c_sptr_pga_db_per_step(*args)
def daughterboard_id(*args):
"""daughterboard_id(self, int which_dboard) -> int"""
return _usrp1.usrp1_source_c_sptr_daughterboard_id(*args)
def set_adc_offset(*args):
"""set_adc_offset(self, int which, int offset) -> bool"""
print "set_adc_offset", args
return _usrp1.usrp1_source_c_sptr_set_adc_offset(*args)
def set_dac_offset(*args):
"""set_dac_offset(self, int which, int offset, int offset_pin) ->
bool"""
print "set_dac_offset", args
return _usrp1.usrp1_source_c_sptr_set_dac_offset(*args)
def set_adc_buffer_bypass(*args):
"""set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
print "set_adc_buffer_bypass", args
return _usrp1.usrp1_source_c_sptr_set_adc_buffer_bypass(*args)
def serial_number(*args):
"""serial_number(self) -> string"""
return _usrp1.usrp1_source_c_sptr_serial_number(*args)
def _write_oe(*args):
"""_write_oe(self, int which_dboard, int value, int mask) -> bool"""
print "_write_oe",args
return _usrp1.usrp1_source_c_sptr__write_oe(*args)
def write_io(*args):
"""write_io(self, int which_dboard, int value, int mask) -> bool"""
print "_write_io",args
return _usrp1.usrp1_source_c_sptr_write_io(*args)
def read_io(*args):
"""read_io(self, int which_dboard) -> int"""
return _usrp1.usrp1_source_c_sptr_read_io(*args)
def set_dc_offset_cl_enable(*args):
"""set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
print "set_dc_offset_cl_enable", args
return _usrp1.usrp1_source_c_sptr_set_dc_offset_cl_enable(*args)
def set_format(*args):
"""set_format(self, unsigned int format) -> bool"""
print "set_format", args
return _usrp1.usrp1_source_c_sptr_set_format(*args)
def format(*args):
"""format(self) -> unsigned int"""
return _usrp1.usrp1_source_c_sptr_format(*args)
def make_format(*args):
"""
make_format(self, int width=16, int shift=0, bool want_q=True, bool
bypass_halfband=False) -> unsigned int
make_format(self, int width=16, int shift=0, bool want_q=True) ->
unsigned int
make_format(self, int width=16, int shift=0) -> unsigned int
make_format(self, int width=16) -> unsigned int
make_format(self) -> unsigned int
"""
return _usrp1.usrp1_source_c_sptr_make_format(*args)
def format_width(*args):
"""format_width(self, unsigned int format) -> int"""
return _usrp1.usrp1_source_c_sptr_format_width(*args)
def format_shift(*args):
"""format_shift(self, unsigned int format) -> int"""
return _usrp1.usrp1_source_c_sptr_format_shift(*args)
def format_want_q(*args):
"""format_want_q(self, unsigned int format) -> bool"""
return _usrp1.usrp1_source_c_sptr_format_want_q(*args)
def format_bypass_halfband(*args):
"""format_bypass_halfband(self, unsigned int format) -> bool"""
return _usrp1.usrp1_source_c_sptr_format_bypass_halfband(*args)
def write_aux_dac(*args):
"""write_aux_dac(self, int which_dboard, int which_dac, int value) ->
bool"""
print "write_aux_dac",args
return _usrp1.usrp1_source_c_sptr_write_aux_dac(*args)
def read_aux_adc(*args):
"""read_aux_adc(self, int which_dboard, int which_adc) -> int"""
return _usrp1.usrp1_source_c_sptr_read_aux_adc(*args)
def write_eeprom(*args):
"""write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) ->
bool"""
print "write_eeprom",args
return _usrp1.usrp1_source_c_sptr_write_eeprom(*args)
def read_eeprom(*args):
"""read_eeprom(self, int i2c_addr, int eeprom_offset, int len) ->
string"""
return _usrp1.usrp1_source_c_sptr_read_eeprom(*args)
def write_i2c(*args):
"""write_i2c(self, int i2c_addr, string buf) -> bool"""
print "write_i2c",args
return _usrp1.usrp1_source_c_sptr_write_i2c(*args)
def read_i2c(*args):
"""read_i2c(self, int i2c_addr, int len) -> string"""
return _usrp1.usrp1_source_c_sptr_read_i2c(*args)
def _write_fpga_reg(*args):
"""_write_fpga_reg(self, int regno, int value) -> bool"""
print "_write_fpga_reg",args
return _usrp1.usrp1_source_c_sptr__write_fpga_reg(*args)
def _write_fpga_reg_masked(*args):
"""_write_fpga_reg_masked(self, int regno, int value, int mask) ->
bool"""
print "_write_fpga_reg_masked",args
return _usrp1.usrp1_source_c_sptr__write_fpga_reg_masked(*args)
def _read_fpga_reg(*args):
"""_read_fpga_reg(self, int regno) -> int"""
return _usrp1.usrp1_source_c_sptr__read_fpga_reg(*args)
def _write_9862(*args):
"""_write_9862(self, int which_codec, int regno, unsigned char value)
-> bool"""
print "_write_9862",args
return _usrp1.usrp1_source_c_sptr__write_9862(*args)
def _read_9862(*args):
"""_read_9862(self, int which_codec, int regno) -> int"""
return _usrp1.usrp1_source_c_sptr__read_9862(*args)
def _write_spi(*args):
"""_write_spi(self, int optional_header, int enables, int format,
string buf) -> bool"""
print "_write_spi",args
return _usrp1.usrp1_source_c_sptr__write_spi(*args)
def _read_spi(*args):
"""_read_spi(self, int optional_header, int enables, int format, int
len) -> string"""
return _usrp1.usrp1_source_c_sptr__read_spi(*args)
def history(*args):
"""history(self) -> unsigned int"""
return _usrp1.usrp1_source_c_sptr_history(*args)
def output_multiple(*args):
"""output_multiple(self) -> int"""
return _usrp1.usrp1_source_c_sptr_output_multiple(*args)
def relative_rate(*args):
"""relative_rate(self) -> double"""
return _usrp1.usrp1_source_c_sptr_relative_rate(*args)
def start(*args):
"""start(self) -> bool"""
return _usrp1.usrp1_source_c_sptr_start(*args)
def stop(*args):
"""stop(self) -> bool"""
return _usrp1.usrp1_source_c_sptr_stop(*args)
def detail(*args):
"""detail(self) -> gr_block_detail_sptr"""
return _usrp1.usrp1_source_c_sptr_detail(*args)
def set_detail(*args):
"""set_detail(self, gr_block_detail_sptr detail)"""
print "set_detail", args
return _usrp1.usrp1_source_c_sptr_set_detail(*args)
def name(*args):
"""name(self) -> string"""
return _usrp1.usrp1_source_c_sptr_name(*args)
def input_signature(*args):
"""input_signature(self) -> gr_io_signature_sptr"""
return _usrp1.usrp1_source_c_sptr_input_signature(*args)
def output_signature(*args):
"""output_signature(self) -> gr_io_signature_sptr"""
return _usrp1.usrp1_source_c_sptr_output_signature(*args)
def unique_id(*args):
"""unique_id(self) -> long"""
return _usrp1.usrp1_source_c_sptr_unique_id(*args)
def basic_block(*args):
"""basic_block(self) -> gr_basic_block_sptr"""
return _usrp1.usrp1_source_c_sptr_basic_block(*args)
def check_topology(*args):
"""check_topology(self, int ninputs, int noutputs) -> bool"""
return _usrp1.usrp1_source_c_sptr_check_topology(*args)
usrp1_source_c_sptr_swigregister = _usrp1.usrp1_source_c_sptr_swigregister
usrp1_source_c_sptr_swigregister(usrp1_source_c_sptr)
def usrp1_source_c_block(*args):
"""usrp1_source_c_block(usrp1_source_c_sptr r) -> gr_block_sptr"""
return _usrp1.usrp1_source_c_block(*args)
usrp1_source_c_sptr.block = lambda self: usrp1_source_c_block (self)
usrp1_source_c_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" %
(self.name(), self.unique_id ())
def source_c(*args):
"""
source_c(int which_board, unsigned int decim_rate, int nchan,
int mux, int mode, int fusb_block_size, int fusb_nblocks,
string fpga_filename, string firmware_filename) -> usrp1_source_c_sptr
"""
return _usrp1.source_c(*args)
class usrp1_source_s_sptr(object):
"""Proxy of C++ usrp1_source_s_sptr class"""
thisown = _swig_property(lambda x: x.this.own(), lambda x, v:
x.this.own(v), doc='The membership flag')
__repr__ = _swig_repr
def __init__(self, *args):
"""
__init__(self) -> usrp1_source_s_sptr
__init__(self, p) -> usrp1_source_s_sptr
"""
this = _usrp1.new_usrp1_source_s_sptr(*args)
try: self.this.append(this)
except: self.this = this
def __deref__(*args):
"""__deref__(self)"""
return _usrp1.usrp1_source_s_sptr___deref__(*args)
__swig_destroy__ = _usrp1.delete_usrp1_source_s_sptr
__del__ = lambda self : None;
def set_decim_rate(*args):
"""set_decim_rate(self, unsigned int rate) -> bool"""
print "set_decim_rate", args
return _usrp1.usrp1_source_s_sptr_set_decim_rate(*args)
def set_nchannels(*args):
"""set_nchannels(self, int nchan) -> bool"""
print "set_nchannels", args
return _usrp1.usrp1_source_s_sptr_set_nchannels(*args)
def set_mux(*args):
"""set_mux(self, int mux) -> bool"""
print "set_mux", args
return _usrp1.usrp1_source_s_sptr_set_mux(*args)
def set_rx_freq(*args):
"""set_rx_freq(self, int channel, double freq) -> bool"""
print "set_rx_freq", args
return _usrp1.usrp1_source_s_sptr_set_rx_freq(*args)
def set_fpga_mode(*args):
"""set_fpga_mode(self, int mode) -> bool"""
print "set_fpga_mode", args
return _usrp1.usrp1_source_s_sptr_set_fpga_mode(*args)
def set_ddc_phase(*args):
"""set_ddc_phase(self, int channel, int phase) -> bool"""
print "set_ddc_phase", args
return _usrp1.usrp1_source_s_sptr_set_ddc_phase(*args)
def set_verbose(*args):
"""set_verbose(self, bool verbose)"""
print "set_verbose", args
return _usrp1.usrp1_source_s_sptr_set_verbose(*args)
def fpga_master_clock_freq(*args):
"""fpga_master_clock_freq(self) -> long"""
return _usrp1.usrp1_source_s_sptr_fpga_master_clock_freq(*args)
def converter_rate(*args):
"""converter_rate(self) -> long"""
return _usrp1.usrp1_source_s_sptr_converter_rate(*args)
def adc_rate(*args):
"""adc_rate(self) -> long"""
return _usrp1.usrp1_source_s_sptr_adc_rate(*args)
def adc_freq(*args):
"""adc_freq(self) -> long"""
return _usrp1.usrp1_source_s_sptr_adc_freq(*args)
def decim_rate(*args):
"""decim_rate(self) -> unsigned int"""
return _usrp1.usrp1_source_s_sptr_decim_rate(*args)
def rx_freq(*args):
"""rx_freq(self, int channel) -> double"""
return _usrp1.usrp1_source_s_sptr_rx_freq(*args)
def noverruns(*args):
"""noverruns(self) -> int"""
return _usrp1.usrp1_source_s_sptr_noverruns(*args)
def set_pga(*args):
"""set_pga(self, int which, double gain_in_db) -> bool"""
print "set_pga", args
return _usrp1.usrp1_source_s_sptr_set_pga(*args)
def pga(*args):
"""pga(self, int which) -> double"""
return _usrp1.usrp1_source_s_sptr_pga(*args)
def pga_min(*args):
"""pga_min(self) -> double"""
return _usrp1.usrp1_source_s_sptr_pga_min(*args)
def pga_max(*args):
"""pga_max(self) -> double"""
return _usrp1.usrp1_source_s_sptr_pga_max(*args)
def pga_db_per_step(*args):
"""pga_db_per_step(self) -> double"""
return _usrp1.usrp1_source_s_sptr_pga_db_per_step(*args)
def daughterboard_id(*args):
"""daughterboard_id(self, int which_dboard) -> int"""
return _usrp1.usrp1_source_s_sptr_daughterboard_id(*args)
def set_adc_offset(*args):
"""set_adc_offset(self, int which, int offset) -> bool"""
print "set_adc_offset", args
return _usrp1.usrp1_source_s_sptr_set_adc_offset(*args)
def set_dac_offset(*args):
"""set_dac_offset(self, int which, int offset, int offset_pin) ->
bool"""
print "set_dac_offset", args
return _usrp1.usrp1_source_s_sptr_set_dac_offset(*args)
def set_adc_buffer_bypass(*args):
"""set_adc_buffer_bypass(self, int which, bool bypass) -> bool"""
print "set_adc_buffer_bypass", args
return _usrp1.usrp1_source_s_sptr_set_adc_buffer_bypass(*args)
def serial_number(*args):
"""serial_number(self) -> string"""
return _usrp1.usrp1_source_s_sptr_serial_number(*args)
def _write_oe(*args):
"""_write_oe(self, int which_dboard, int value, int mask) -> bool"""
print "_write_oe",args
return _usrp1.usrp1_source_s_sptr__write_oe(*args)
def write_io(*args):
"""write_io(self, int which_dboard, int value, int mask) -> bool"""
print "_write_io",args
return _usrp1.usrp1_source_s_sptr_write_io(*args)
def read_io(*args):
"""read_io(self, int which_dboard) -> int"""
return _usrp1.usrp1_source_s_sptr_read_io(*args)
def set_dc_offset_cl_enable(*args):
"""set_dc_offset_cl_enable(self, int bits, int mask) -> bool"""
print "set_dc_offset_cl_enable", args
return _usrp1.usrp1_source_s_sptr_set_dc_offset_cl_enable(*args)
def set_format(*args):
"""set_format(self, unsigned int format) -> bool"""
print "set_format", args
return _usrp1.usrp1_source_s_sptr_set_format(*args)
def format(*args):
"""format(self) -> unsigned int"""
return _usrp1.usrp1_source_s_sptr_format(*args)
def make_format(*args):
"""
make_format(self, int width=16, int shift=0, bool want_q=True, bool
bypass_halfband=False) -> unsigned int
make_format(self, int width=16, int shift=0, bool want_q=True) ->
unsigned int
make_format(self, int width=16, int shift=0) -> unsigned int
make_format(self, int width=16) -> unsigned int
make_format(self) -> unsigned int
"""
return _usrp1.usrp1_source_s_sptr_make_format(*args)
def format_width(*args):
"""format_width(self, unsigned int format) -> int"""
return _usrp1.usrp1_source_s_sptr_format_width(*args)
def format_shift(*args):
"""format_shift(self, unsigned int format) -> int"""
return _usrp1.usrp1_source_s_sptr_format_shift(*args)
def format_want_q(*args):
"""format_want_q(self, unsigned int format) -> bool"""
return _usrp1.usrp1_source_s_sptr_format_want_q(*args)
def format_bypass_halfband(*args):
"""format_bypass_halfband(self, unsigned int format) -> bool"""
return _usrp1.usrp1_source_s_sptr_format_bypass_halfband(*args)
def write_aux_dac(*args):
"""write_aux_dac(self, int which_dboard, int which_dac, int value) ->
bool"""
print "write_aux_dac",args
return _usrp1.usrp1_source_s_sptr_write_aux_dac(*args)
def read_aux_adc(*args):
"""read_aux_adc(self, int which_dboard, int which_adc) -> int"""
return _usrp1.usrp1_source_s_sptr_read_aux_adc(*args)
def write_eeprom(*args):
"""write_eeprom(self, int i2c_addr, int eeprom_offset, string buf) ->
bool"""
print "write_eeprom",args
return _usrp1.usrp1_source_s_sptr_write_eeprom(*args)
def read_eeprom(*args):
"""read_eeprom(self, int i2c_addr, int eeprom_offset, int len) ->
string"""
return _usrp1.usrp1_source_s_sptr_read_eeprom(*args)
def write_i2c(*args):
"""write_i2c(self, int i2c_addr, string buf) -> bool"""
print "write_i2c",args
return _usrp1.usrp1_source_s_sptr_write_i2c(*args)
def read_i2c(*args):
"""read_i2c(self, int i2c_addr, int len) -> string"""
return _usrp1.usrp1_source_s_sptr_read_i2c(*args)
def _write_fpga_reg(*args):
"""_write_fpga_reg(self, int regno, int value) -> bool"""
print "_write_fpga_reg",args
return _usrp1.usrp1_source_s_sptr__write_fpga_reg(*args)
def _write_fpga_reg_masked(*args):
"""_write_fpga_reg_masked(self, int regno, int value, int mask) ->
bool"""
print "_write_fpga_reg_masked",args
return _usrp1.usrp1_source_s_sptr__write_fpga_reg_masked(*args)
def _read_fpga_reg(*args):
"""_read_fpga_reg(self, int regno) -> int"""
return _usrp1.usrp1_source_s_sptr__read_fpga_reg(*args)
def _write_9862(*args):
"""_write_9862(self, int which_codec, int regno, unsigned char value)
-> bool"""
print "_write_9862",args
return _usrp1.usrp1_source_s_sptr__write_9862(*args)
def _read_9862(*args):
"""_read_9862(self, int which_codec, int regno) -> int"""
return _usrp1.usrp1_source_s_sptr__read_9862(*args)
def _write_spi(*args):
"""_write_spi(self, int optional_header, int enables, int format,
string buf) -> bool"""
print "_write_spi",args
return _usrp1.usrp1_source_s_sptr__write_spi(*args)
def _read_spi(*args):
"""_read_spi(self, int optional_header, int enables, int format, int
len) -> string"""
return _usrp1.usrp1_source_s_sptr__read_spi(*args)
def history(*args):
"""history(self) -> unsigned int"""
return _usrp1.usrp1_source_s_sptr_history(*args)
def output_multiple(*args):
"""output_multiple(self) -> int"""
return _usrp1.usrp1_source_s_sptr_output_multiple(*args)
def relative_rate(*args):
"""relative_rate(self) -> double"""
return _usrp1.usrp1_source_s_sptr_relative_rate(*args)
def start(*args):
"""start(self) -> bool"""
return _usrp1.usrp1_source_s_sptr_start(*args)
def stop(*args):
"""stop(self) -> bool"""
return _usrp1.usrp1_source_s_sptr_stop(*args)
def detail(*args):
"""detail(self) -> gr_block_detail_sptr"""
return _usrp1.usrp1_source_s_sptr_detail(*args)
def set_detail(*args):
"""set_detail(self, gr_block_detail_sptr detail)"""
print "set_detail", args
return _usrp1.usrp1_source_s_sptr_set_detail(*args)
def name(*args):
"""name(self) -> string"""
return _usrp1.usrp1_source_s_sptr_name(*args)
def input_signature(*args):
"""input_signature(self) -> gr_io_signature_sptr"""
return _usrp1.usrp1_source_s_sptr_input_signature(*args)
def output_signature(*args):
"""output_signature(self) -> gr_io_signature_sptr"""
return _usrp1.usrp1_source_s_sptr_output_signature(*args)
def unique_id(*args):
"""unique_id(self) -> long"""
return _usrp1.usrp1_source_s_sptr_unique_id(*args)
def basic_block(*args):
"""basic_block(self) -> gr_basic_block_sptr"""
return _usrp1.usrp1_source_s_sptr_basic_block(*args)
def check_topology(*args):
"""check_topology(self, int ninputs, int noutputs) -> bool"""
return _usrp1.usrp1_source_s_sptr_check_topology(*args)
usrp1_source_s_sptr_swigregister = _usrp1.usrp1_source_s_sptr_swigregister
usrp1_source_s_sptr_swigregister(usrp1_source_s_sptr)
def usrp1_source_s_block(*args):
"""usrp1_source_s_block(usrp1_source_s_sptr r) -> gr_block_sptr"""
return _usrp1.usrp1_source_s_block(*args)
usrp1_source_s_sptr.block = lambda self: usrp1_source_s_block (self)
usrp1_source_s_sptr.__repr__ = lambda self: "<gr_block %s (%d)>" %
(self.name(), self.unique_id ())
def source_s(*args):
"""
source_s(int which_board, unsigned int decim_rate, int nchan,
int mux, int mode, int fusb_block_size, int fusb_nblocks,
string fpga_filename, string firmware_filename) -> usrp1_source_s_sptr
"""
return _usrp1.source_s(*args)