Re: [Discuss-gnuradio] Daughter board pins

[Eric Blossom]

On Tue, Sep 26, 2006 at 03:15:16PM +0100, Andrew Borg wrote:

> Hi Oussama. I managed to get the signals I want out of my daughter
> board (BasicRX) on RxA. So thanks a lot for your help (and by proxy
> to Eric too!). However, I have one more problem. I need to get some
> other signals out from the FPGA on my other daughterboard that is on
> the board marked RxB. The Verilog code I can handle - no problems
> there. What I am unsure about is the python code. So far I have the
> following code which outputs the signals I need from RxA:

> 
>  u = usrp.sink_c(0, 64)
>  u._write_oe(0, 0xffff, 0xffff) 

Note that this is output enabling the pins on the TX_A daugterboard.
Is that what you wanted?  I hope so ;)
It's the TX_A because you opened the sink_c, and you're passing 0 as
the "which" argument to _write_oe


Assuming you've got two Basic Rx d'boards installed, one on the A side
and one on the B side, you'll want:

  u = usrp.source_c(0, 64)          # note that we're opening the source
  u._write_oe(0, 0xffff, 0xffff) 
  u._write_oe(1, 0xffff, 0xffff) 
  u._write_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_RX_A | bmFR_DEBUG_EN_RX_B) 


>  u._write_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_RX_A)
> 
> The above is basically what you sent me. Now if I change the last line to : 
> 


> then I still get the signals I need from RxA but still nothing from
> RX_B (I've changed the Verilog code as required - I understand that
> part fine). I also tried adding u._write_oe(1, 0xffff, 0xffff) but
> it still does not work. This latest try is a stab in the dark and
> I'm afraid to go further without asking because of the worrying
> comments before the _write_oe function!! I was tempted to move the
> daughter board to a TX slot but was afraid of cooking the board.

Being afraid of cooking the board is a good thing to have on your mind ;)
The Tx and Rx boards are _NOT_ interchangable.  Don't try it.

If this doesn't help, you might want to take another look at your
verilog.  Perhaps you're connecting your debug output to the wrong
pins?


debug_0 is TX_A
debug_1 is RX_A
debug_2 is TX_B
debug_3 is RX_B



   wire [15:0] reg_0,reg_1,reg_2,reg_3;
   master_control master_control
     ( .master_clk(clk64),.usbclk(usbclk),
       
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
       .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
       .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
       .enable_tx(enable_tx),.enable_rx(enable_rx),
       .interp_rate(interp_rate),.decim_rate(decim_rate),
       .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
       .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
       .tx_empty(tx_empty),
       //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
       .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
       
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
       .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
   

Eric