RE: [Discuss-gnuradio] Queries regarding FPGA

[Clark Pope]

You'll want to strip out the extra receiver. The default fpga is 2 rx and 1 
tx. You probably don't need the second RX for your application. You also may 
not need the halfband filter on your receiver.

In the past I've stripped down to a single RX and got utilization down to 
about 30%. You'll probably be at 40% with one RX and one TX.

As far as control logic. I've been planning something similar (open 802.11 
mac) and I was thinking I could write a linux device driver to do a lot of 
the time critical stuff (agc, CA, etc.). Seems like one can poll some status 
lines from the FPGA frequently enough to do a lot of things.

----Original Message Follows----
From: "amit malani" <address@hidden>
Reply-To: address@hidden
To: address@hidden
Subject: [Discuss-gnuradio] Queries regarding FPGA
Date: Sat, 25 Feb 2006 23:06:57 -0500

Hello!
I am trying to implement a CSMA/CA typish MAC layer protocol. something like
RTS-CTS-DATA-ACK type packet exchange.  The idea to move some functionality
on FPGA.
The idea is to maintain two speperate buffers, one for DATA packets and the
other for  RTS packets. so that over multiple rounds of transmissions,
DATA  packet is preprocessed and stored on FPGA..yeilding in good deal of
time saving.

Also implementing some timers on FPGA which would assist in collision
avoidance mechanism.

I just wanted a sanity check from you guys who have worked on design and use
of FPGA.



on a course level i could see, from std_usrp project,

57% of the memory bits are utilised so far: there is scope for extra buffer
87% of LEs are  also utilised. :

So would there be enough space to implement the control logic? (will need to
implement inside the master_control module right?).
if there is not enough space, can I kick out few modules?
Also how control signaling is done?...it must be inline to data path I
guess? whats the protocol for it?


thanks,
amit


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