[Commit-gnuradio] r10521 - in gnuradio/trunk/usrp2: firmware/lib fpga/top/u2_core

[matt]

Author: matt
Date: 2009-02-25 21:27:08 -0700 (Wed, 25 Feb 2009)
New Revision: 10521

Modified:
   gnuradio/trunk/usrp2/firmware/lib/db_dbsrx.c
   gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v
Log:
remove support for unmodified dbsrx because there is way too much phase noise.  
only modified dbsrx are supported


Modified: gnuradio/trunk/usrp2/firmware/lib/db_dbsrx.c
===================================================================
--- gnuradio/trunk/usrp2/firmware/lib/db_dbsrx.c        2009-02-26 03:58:45 UTC 
(rev 10520)
+++ gnuradio/trunk/usrp2/firmware/lib/db_dbsrx.c        2009-02-26 04:27:08 UTC 
(rev 10521)
@@ -69,10 +69,10 @@
 };
 
 struct db_dbsrx db_dbsrx = {
-  .base.dbid = 0x0002,
+  .base.dbid = 0x000d,
   .base.is_tx = false,
-  .base.output_enables = 0x0001,
-  .base.used_pins = 0x0001,
+  .base.output_enables = 0x0000,
+  .base.used_pins = 0x0000,
   .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(500e6),
   .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2.6e9),
   .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
@@ -111,9 +111,6 @@
   db->base.set_gain(dbb, (db->base.gain_max + db->base.gain_min)/2);
   clocks_enable_rx_dboard(true, REFCLK_DIVISOR);  // Gives 4 MHz clock
 
-  hal_gpio_set_sel(GPIO_RX_BANK, 0, '1');
-
-
   return true;
 }
 

Modified: gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v     2009-02-26 03:58:45 UTC 
(rev 10520)
+++ gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v     2009-02-26 04:27:08 UTC 
(rev 10521)
@@ -375,18 +375,10 @@
    assign       s3_rty = 1'b0;
    
    // GPIOs -- Slave #4
-   reg [4:0]    dbsrx_ctr;
-   reg                  dbsrx_clk;
-   always @(posedge dsp_clk)
-     if(dsp_rst) dbsrx_ctr <= 0;
-     else if(dbsrx_ctr == 24) dbsrx_ctr <= 0;
-     else dbsrx_ctr <= dbsrx_ctr + 1;
-   always @(posedge dsp_clk) dbsrx_clk <= (dbsrx_ctr == 24);
-   
    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
                 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
                 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
-                
.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1({debug_gpio_1[31:1],dbsrx_clk}),
+                .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
                 .gpio( {io_tx,io_rx} ) );
    assign       s4_err = 1'b0;
    assign       s4_rty = 1'b0;