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[Commit-gnuradio] r10405 - gnuradio/branches/releases/3.2/usrp2/firmware
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From: |
jcorgan |
|
Subject: |
[Commit-gnuradio] r10405 - gnuradio/branches/releases/3.2/usrp2/firmware/lib |
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Date: |
Sun, 8 Feb 2009 13:06:16 -0700 (MST) |
Author: jcorgan
Date: 2009-02-08 13:06:15 -0700 (Sun, 08 Feb 2009)
New Revision: 10405
Modified:
gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_dbsrx.c
gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_init.c
gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_rfx.c
gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_xcvr2450.c
Log:
Merged r10375, r10377, r10382, r10387 from trunk into release-3.2 branch
Modified: gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_dbsrx.c
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_dbsrx.c
2009-02-06 19:16:49 UTC (rev 10404)
+++ gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_dbsrx.c
2009-02-08 20:06:15 UTC (rev 10405)
@@ -107,7 +107,7 @@
bool
db_dbsrx_init(struct db_base *dbb){
struct db_dbsrx_dummy *db = (struct db_dbsrx_dummy *) dbb;
- db->base.set_gain(dbb, (db->base.gain_max - db->base.gain_min)/2);
+ db->base.set_gain(dbb, (db->base.gain_max + db->base.gain_min)/2);
clocks_enable_rx_dboard(true, REFCLK_DIVISOR); // Gives 4 MHz clock
return true;
}
@@ -115,7 +115,7 @@
/**************************************************
* Registers
**************************************************/
-int
+static int
_read_adc (void){
unsigned char readback[2];
i2c_read(I2C_ADDR, readback, 2*sizeof(unsigned char));
@@ -125,7 +125,7 @@
return adc_val;
}
-void
+static void
_write_reg (int regno, int v){
//regno is in [0,5], v is value to write to register"""
unsigned char args[2];
@@ -135,66 +135,66 @@
printf("Reg %d, Val %x\n",regno,v);
}
-void _send_reg_0(struct db_dbsrx_dummy *db){
+static void _send_reg_0(struct db_dbsrx_dummy *db){
_write_reg(0,(db->common.d_div2<<7) + (db->common.d_n>>8));
}
-void _send_reg_1(struct db_dbsrx_dummy *db){
+static void _send_reg_1(struct db_dbsrx_dummy *db){
_write_reg(1,db->common.d_n & 255);
}
-void _send_reg_2(struct db_dbsrx_dummy *db){
+static void _send_reg_2(struct db_dbsrx_dummy *db){
_write_reg(2,db->common.d_osc + (db->common.d_cp<<3) +
(db->common.d_r_reg<<5));
}
-void _send_reg_3(struct db_dbsrx_dummy *db){
+static void _send_reg_3(struct db_dbsrx_dummy *db){
_write_reg(3,db->common.d_fdac);
}
-void _send_reg_4(struct db_dbsrx_dummy *db){
+static void _send_reg_4(struct db_dbsrx_dummy *db){
_write_reg(4,db->common.d_m + (db->common.d_dl<<5) + (db->common.d_ade<<6) +
(db->common.d_adl<<7));
}
-void _send_reg_5(struct db_dbsrx_dummy *db){
+static void _send_reg_5(struct db_dbsrx_dummy *db){
_write_reg(5,db->common.d_gc2 + (db->common.d_diag<<5));
}
/**************************************************
* Helpers for setting the freq
**************************************************/
-void
+static void
_set_div2(struct db_dbsrx_dummy *db, int div2){
db->common.d_div2 = div2;
_send_reg_0(db);
}
// FIXME How do we handle ADE and ADL properly?
-void
+static void
_set_ade(struct db_dbsrx_dummy *db, int ade){
db->common.d_ade = ade;
_send_reg_4(db);
}
-void
+static void
_set_r(struct db_dbsrx_dummy *db, int r){
db->common.d_r_reg = r;
_send_reg_2(db);
}
-void
+static void
_set_n(struct db_dbsrx_dummy *db, int n){
db->common.d_n = n;
_send_reg_0(db);
_send_reg_1(db);
}
-void
+static void
_set_osc(struct db_dbsrx_dummy *db, int osc){
db->common.d_osc = osc;
_send_reg_2(db);
}
-void
+static void
_set_cp(struct db_dbsrx_dummy *db, int cp){
db->common.d_cp = cp;
_send_reg_2(db);
@@ -330,7 +330,7 @@
* Helpers for setting the gain
**************************************************/
-void
+static void
_set_gc2(struct db_dbsrx_dummy *db, int gc2){
db->common.d_gc2 = gc2;
_send_reg_5(db);
@@ -380,13 +380,13 @@
/**************************************************
* Helpers for setting the bw
**************************************************/
-void
+static void
_set_m(struct db_dbsrx_dummy *db, int m){
db->common.d_m = m;
_send_reg_4(db);
}
-void
+static void
_set_fdac(struct db_dbsrx_dummy *db, int fdac){
db->common.d_fdac = fdac;
_send_reg_3(db);
Modified: gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_init.c
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_init.c 2009-02-06
19:16:49 UTC (rev 10404)
+++ gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_init.c 2009-02-08
20:06:15 UTC (rev 10405)
@@ -162,7 +162,7 @@
return db;
}
-static void
+void
set_atr_regs(int bank, struct db_base *db)
{
uint32_t val[4];
Modified: gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_rfx.c
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_rfx.c 2009-02-06
19:16:49 UTC (rev 10404)
+++ gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_rfx.c 2009-02-08
20:06:15 UTC (rev 10405)
@@ -488,7 +488,7 @@
*dc = 0;
struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
- u2_fxpt_freq_t desired_n =
((1LL<<20)*db->common.freq_mult*(freq+db->common.freq_offset))/phdet_freq;
+ u2_fxpt_freq_t desired_n =
(U2_DOUBLE_TO_FXPT_FREQ(1.0)*db->common.freq_mult*(freq+db->common.freq_offset))/phdet_freq;
int N_DIV = u2_fxpt_freq_round_to_int(desired_n);
int B = N_DIV/PRESCALER;
int A = N_DIV - PRESCALER*B;
Modified: gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_xcvr2450.c
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_xcvr2450.c
2009-02-06 19:16:49 UTC (rev 10404)
+++ gnuradio/branches/releases/3.2/usrp2/firmware/lib/db_xcvr2450.c
2009-02-08 20:06:15 UTC (rev 10405)
@@ -19,7 +19,12 @@
#include <db_base.h>
#include <stdio.h>
#include <spi.h>
+#include <hal_io.h>
+#include <clocks.h>
+#include <mdelay.h>
+void set_atr_regs(int bank, struct db_base *db); //FIXME I need to be in a
header
+
// RX IO Pins
#define LOCKDET (1 << 15) // This is an INPUT!!!
#define EN (1 << 14)
@@ -34,6 +39,7 @@
#define B7 (1 << 5)
#define RX_OE_MASK EN|RX_EN|RX_HP|B1|B2|B3|B4|B5|B6|B7
#define RX_SAFE_IO EN
+#define RX_ATR_MASK EN|RX_EN|RX_HP
// TX IO Pins
#define HB_PA_OFF (1 << 15) // 5GHz PA, 1 = off, 0 = on
@@ -44,9 +50,14 @@
#define AD9515DIV (1 << 4) // 1 = Div by 3, 0 = Div by 2
#define TX_OE_MASK
HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|ANTSEL_TX2_RX1|TX_EN|AD9515DIV
#define TX_SAFE_IO HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|AD9515DIV
+#define TX_ATR_MASK
HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|ANTSEL_TX2_RX1|TX_EN|AD9515DIV
-#define TUN_FREQ_MIN U2_DOUBLE_TO_FXPT_FREQ(2.4e9)
-#define TUN_FREQ_MAX U2_DOUBLE_TO_FXPT_FREQ(6.0e9)
+#define LB_FREQ_MIN U2_DOUBLE_TO_FXPT_FREQ(2.3e9)
+#define LB_FREQ_MAX U2_DOUBLE_TO_FXPT_FREQ(2.6e9)
+#define HB_FREQ_MIN U2_DOUBLE_TO_FXPT_FREQ(4.8e9)
+#define HB_FREQ_MAX U2_DOUBLE_TO_FXPT_FREQ(6.1e9)
+#define MASTER_REF_CLK_DIV 1
+#define N_DIV_MIN_Q16 (130 << 16)
bool xcvr2450_init(struct db_base *db);
bool xcvr2450_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t
*dc);
@@ -65,306 +76,264 @@
int d_pabias_delay, d_pabias;
int d_rx_rf_gain, d_rx_bb_gain, d_txgain;
int d_ad9515_div;
- int spi_mask;
+ int d_tx_enb;
};
struct db_xcvr2450_dummy {
struct db_base base;
- struct db_xcvr2450_common common;
+ struct db_xcvr2450_common *common;
};
struct db_xcvr2450_rx {
struct db_base base;
- struct db_xcvr2450_common common;
+ struct db_xcvr2450_common *common;
};
struct db_xcvr2450_tx {
struct db_base base;
- struct db_xcvr2450_common common;
+ struct db_xcvr2450_common *common;
};
/*
+ * shared common between rx and tx db
+ */
+struct db_xcvr2450_common db_xcvr2450_common = {
+ /* set sane defaults */
+ .d_mimo = 1, // 0 = OFF, 1 = ON
+ .d_int_div = 192, // 128 = min, 255 = max
+ .d_frac_div = 0, // 0 = min, 65535 = max
+ .d_highband = 0, // 0 = freq <= 5.4e9, 1 = freq > 5.4e9
+ .d_five_gig = 0, // 0 = freq <= 3.e9, 1 = freq > 3e9
+ .d_cp_current = 0, // 0 = 2mA, 1 = 4mA
+ .d_ref_div = 1, // 1 to 7
+ .d_rssi_hbw = 0, // 0 = 2 MHz, 1 = 6 MHz
+ .d_txlpf_bw = 1, // 1 = 12 MHz, 2 = 18 MHz, 3 = 24 MHz
+ .d_rxlpf_bw = 1, // 0 = 7.5 MHz, 1 = 9.5 MHz, 2 = 14 MHz, 3 = 18 MHz
+ .d_rxlpf_fine = 2, // 0 = 90%, 1 = 95%, 2 = 100%, 3 = 105%, 4 = 110%
+ .d_rxvga_ser = 1, // 0 = RXVGA controlled by B7:1, 1=controlled serially
+ .d_rssi_range = 1, // 0 = low range (datasheet typo), 1=high range (0.5V
- 2.0V)
+ .d_rssi_mode = 1, // 0 = enable follows RXHP, 1 = enabled
+ .d_rssi_mux = 0, // 0 = RSSI, 1 = TEMP
+ .d_rx_hp_pin = 0, // 0 = Fc set by rx_hpf, 1 = 600 KHz
+ .d_rx_hpf = 0, // 0 = 100Hz, 1 = 30KHz
+ .d_rx_ant = 0, // 0 = Ant. #1, 1 = Ant. #2
+ .d_tx_ant = 0, // 0 = Ant. #1, 1 = Ant. #2
+ .d_txvga_ser = 1, // 0 = TXVGA controlled by B6:1, 1=controlled serially
+ .d_tx_driver_lin = 2, // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best
lin)
+ .d_tx_vga_lin = 2, // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best
lin)
+ .d_tx_upconv_lin = 2, // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best
lin)
+ .d_tx_bb_gain = 3, // 0=maxgain-5dB, 1=max-3dB, 2=max-1.5dB, 3=max
+ .d_pabias_delay = 15, // 0 = 0, 15 = 7uS
+ .d_pabias = 0, // 0 = 0 uA, 63 = 315uA
+ .d_rx_rf_gain = 0, // 0 = 0dB, 1 = 0dB, 2 = 15dB, 3 = 30dB
+ .d_rx_bb_gain = 16, // 0 = min, 31 = max (0 - 62 dB)
+ .d_txgain = 63, // 0 = min, 63 = max
+ .d_tx_enb = 1, // 0 = disabled, 1 = enabled
+};
+
+/*
* The class instances
*/
struct db_xcvr2450_rx db_xcvr2450_rx = {
.base.dbid = 0x0061,
.base.is_tx = false,
.base.output_enables = RX_OE_MASK,
- .base.used_pins = RX_SAFE_IO,
- .base.freq_min = TUN_FREQ_MIN,
- .base.freq_max = TUN_FREQ_MAX,
+ .base.used_pins = 0xFFFF,
+ .base.freq_min = LB_FREQ_MIN,
+ .base.freq_max = HB_FREQ_MAX,
.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(92),
.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(1),
.base.is_quadrature = true,
- .base.i_and_q_swapped = true,
+ .base.i_and_q_swapped = false,
.base.spectrum_inverted = false,
- //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4.25e6),
.base.init = xcvr2450_init,
.base.set_freq = xcvr2450_set_freq,
.base.set_gain = xcvr2450_set_gain_rx,
- .base.set_tx_enable = 0,
- .base.atr_mask = 0x00E0, //CHECK this
- //.base.atr_txval = POWER_UP,
- //.base.atr_rxval = POWER_UP|MIX_EN,
- // .base.atr_tx_delay =
- // .base.atr_rx_delay =
- .common.spi_mask = SPI_SS_RX_DB,
+ .base.atr_mask = RX_ATR_MASK,
+ .base.atr_txval = 0x0,
+ .base.atr_rxval = 0x0,
+ .common = &db_xcvr2450_common,
};
struct db_xcvr2450_tx db_xcvr2450_tx = {
.base.dbid = 0x0060,
.base.is_tx = true,
.base.output_enables = TX_OE_MASK,
- .base.used_pins = TX_SAFE_IO,
- .base.freq_min = TUN_FREQ_MIN,
- .base.freq_max = TUN_FREQ_MAX,
+ .base.used_pins = 0xFFFF,
+ .base.freq_min = LB_FREQ_MIN,
+ .base.freq_max = HB_FREQ_MAX,
.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(30),
.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(30.0/63.0),
.base.is_quadrature = true,
.base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
- //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4.25e6),
.base.init = xcvr2450_init,
.base.set_freq = xcvr2450_set_freq,
.base.set_gain = xcvr2450_set_gain_tx,
.base.set_tx_enable = xcvr2450_set_tx_enable,
- .base.atr_mask = 0x00E0, //CHECK this
- //.base.atr_txval = POWER_UP|MIX_EN,
- //.base.atr_rxval = POWER_UP|ANT_SW,
- // .base.atr_tx_delay =
- // .base.atr_rx_delay =
- .common.spi_mask = SPI_SS_TX_DB,
+ .base.atr_mask = TX_ATR_MASK,
+ .base.atr_txval = 0x0,
+ .base.atr_rxval = 0x0,
+ .common = &db_xcvr2450_common,
};
/**************************************************
* Set Registers
**************************************************/
-void
-send_reg(struct db_xcvr2450_dummy *db, int v){
+static void
+send_reg(int v){
// Send 24 bits, it keeps last 18 clocked in
- spi_transact(SPI_TXONLY,db->common.spi_mask,v,24,SPIF_PUSH_FALL);
- printf("xcvr2450: Setting reg %d to %06X\n", (v&15), v);
+ spi_transact(SPI_TXONLY,SPI_SS_RX_DB,v,24,SPIF_PUSH_FALL);
+ //printf("xcvr2450: Setting reg %d to %x\n", (v&15), v);
}
-void
+static void
set_reg_standby(struct db_xcvr2450_dummy *db){
int reg_standby = (
- (db->common.d_mimo<<17) |
+ (db->common->d_mimo<<17) |
(1<<16) |
(1<<6) |
(1<<5) |
(1<<4) | 2);
- send_reg(db, reg_standby);
+ send_reg(reg_standby);
}
-void
+static void
set_reg_int_divider(struct db_xcvr2450_dummy *db){
- int reg_int_divider = (((db->common.d_frac_div & 0x03)<<16) |
- (db->common.d_int_div<<4) | 3);
- send_reg(db, reg_int_divider);
+ int reg_int_divider = ((
+ (db->common->d_frac_div & 0x03)<<16) |
+ (db->common->d_int_div<<4) | 3);
+ send_reg(reg_int_divider);
}
-void
+static void
set_reg_frac_divider(struct db_xcvr2450_dummy *db){
- int reg_frac_divider = ((db->common.d_frac_div & 0xfffc)<<2) | 4;
- send_reg(db, reg_frac_divider);
+ int reg_frac_divider = ((db->common->d_frac_div & 0xfffc)<<2) | 4;
+ send_reg(reg_frac_divider);
}
-void
+static void
set_reg_bandselpll(struct db_xcvr2450_dummy *db){
- int reg_bandselpll = ((db->common.d_mimo<<17) |
+ int reg_bandselpll = ((db->common->d_mimo<<17) |
(1<<16) |
(1<<15) |
+ (0<<11) | //this bit gets toggled
+ (db->common->d_highband<<10) |
+ (db->common->d_cp_current<<9) |
+ (db->common->d_ref_div<<5) |
+ (db->common->d_five_gig<<4) | 5);
+ send_reg(reg_bandselpll);
+ reg_bandselpll = ((db->common->d_mimo<<17) |
+ (1<<16) |
+ (1<<15) |
(1<<11) |
- (db->common.d_highband<<10) |
- (db->common.d_cp_current<<9) |
- (db->common.d_ref_div<<5) |
- (db->common.d_five_gig<<4) | 5);
- send_reg(db, reg_bandselpll);
+ (db->common->d_highband<<10) |
+ (db->common->d_cp_current<<9) |
+ (db->common->d_ref_div<<5) |
+ (db->common->d_five_gig<<4) | 5);
+ send_reg(reg_bandselpll);
}
-void
+static void
set_reg_cal(struct db_xcvr2450_dummy *db){
// FIXME do calibration
int reg_cal = (
(1<<14) | 6);
- send_reg(db, reg_cal);
+ send_reg(reg_cal);
}
-void
+static void
set_reg_lpf(struct db_xcvr2450_dummy *db){
int reg_lpf = (
- (db->common.d_rssi_hbw<<15) |
- (db->common.d_txlpf_bw<<10) |
- (db->common.d_rxlpf_bw<<9) |
- (db->common.d_rxlpf_fine<<4) | 7);
- send_reg(db, reg_lpf);
+ (db->common->d_rssi_hbw<<15) |
+ (db->common->d_txlpf_bw<<10) |
+ (db->common->d_rxlpf_bw<<9) |
+ (db->common->d_rxlpf_fine<<4) | 7);
+ send_reg(reg_lpf);
}
-void
+static void
set_reg_rxrssi_ctrl(struct db_xcvr2450_dummy *db){
int reg_rxrssi_ctrl = (
- (db->common.d_rxvga_ser<<16) |
- (db->common.d_rssi_range<<15) |
- (db->common.d_rssi_mode<<14) |
- (db->common.d_rssi_mux<<12) |
+ (db->common->d_rxvga_ser<<16) |
+ (db->common->d_rssi_range<<15) |
+ (db->common->d_rssi_mode<<14) |
+ (db->common->d_rssi_mux<<12) |
(1<<9) |
- (db->common.d_rx_hpf<<6) |
+ (db->common->d_rx_hpf<<6) |
(1<<4) | 8);
- send_reg(db, reg_rxrssi_ctrl);
+ send_reg(reg_rxrssi_ctrl);
}
-void
+static void
set_reg_txlin_gain(struct db_xcvr2450_dummy *db){
int reg_txlin_gain = (
- (db->common.d_txvga_ser<<14) |
- (db->common.d_tx_driver_lin<<12) |
- (db->common.d_tx_vga_lin<<10) |
- (db->common.d_tx_upconv_lin<<6) |
- (db->common.d_tx_bb_gain<<4) | 9);
- send_reg(db, reg_txlin_gain);
+ (db->common->d_txvga_ser<<14) |
+ (db->common->d_tx_driver_lin<<12) |
+ (db->common->d_tx_vga_lin<<10) |
+ (db->common->d_tx_upconv_lin<<6) |
+ (db->common->d_tx_bb_gain<<4) | 9);
+ send_reg(reg_txlin_gain);
}
-void
+static void
set_reg_pabias(struct db_xcvr2450_dummy *db){
int reg_pabias = (
- (db->common.d_pabias_delay<<10) |
- (db->common.d_pabias<<4) | 10);
- send_reg(db, reg_pabias);
+ (db->common->d_pabias_delay<<10) |
+ (db->common->d_pabias<<4) | 10);
+ send_reg(reg_pabias);
}
-void
+static void
set_reg_rxgain(struct db_xcvr2450_dummy *db){
int reg_rxgain = (
- (db->common.d_rx_rf_gain<<9) |
- (db->common.d_rx_bb_gain<<4) | 11);
- send_reg(db, reg_rxgain);
+ (db->common->d_rx_rf_gain<<9) |
+ (db->common->d_rx_bb_gain<<4) | 11);
+ send_reg(reg_rxgain);
}
-void
+static void
set_reg_txgain(struct db_xcvr2450_dummy *db){
int reg_txgain = (
- (db->common.d_txgain<<4) | 12);
- send_reg(db, reg_txgain);
+ (db->common->d_txgain<<4) | 12);
+ send_reg(reg_txgain);
}
/**************************************************
* GPIO
**************************************************/
-void
+static void
set_gpio(struct db_xcvr2450_dummy *db){
- // We calculate four values:
- //
- // io_rx_while_rx: what to drive onto io_rx_* when receiving
- // io_rx_while_tx: what to drive onto io_rx_* when transmitting
- // io_tx_while_rx: what to drive onto io_tx_* when receiving
- // io_tx_while_tx: what to drive onto io_tx_* when transmitting
- //
- // B1-B7 is ignored as gain is set serially for now.
+ //set tx/rx gpio pins for auto tr
+ int tx_enb_sel = (db->common->d_tx_enb)? TX_EN:0;
+ int ad9515_sel = (db->common->d_ad9515_div == 3)? AD9515DIV:0;
+ int rx_hp = (db->common->d_rx_hp_pin)? RX_HP:0;
+ int tx_antsel = (db->common->d_tx_ant)? ANTSEL_TX2_RX1:ANTSEL_TX1_RX2;
+ int rx_antsel = (db->common->d_rx_ant)? ANTSEL_TX2_RX1:ANTSEL_TX1_RX2;
+ int tx_pa_sel = (db->common->d_five_gig)? LB_PA_OFF:HB_PA_OFF;
- int rx_hp, tx_antsel, rx_antsel, tx_pa_sel;
- if(db->common.d_rx_hp_pin)
- rx_hp = RX_HP;
- else
- rx_hp = 0;
-
- if(db->common.d_tx_ant)
- tx_antsel = ANTSEL_TX2_RX1;
- else
- tx_antsel = ANTSEL_TX1_RX2;
-
- if(db->common.d_rx_ant)
- rx_antsel = ANTSEL_TX2_RX1;
- else
- rx_antsel = ANTSEL_TX1_RX2;
-
- if(db->common.d_five_gig)
- tx_pa_sel = LB_PA_OFF;
- else
- tx_pa_sel = HB_PA_OFF;
-
- int io_rx_while_rx = EN|rx_hp|RX_EN;
- int io_rx_while_tx = EN|rx_hp;
- int io_tx_while_rx = HB_PA_OFF|LB_PA_OFF|rx_antsel|AD9515DIV;
- int io_tx_while_tx = tx_pa_sel|tx_antsel|TX_EN|AD9515DIV;
- //rx_set_atr_rxval(io_rx_while_rx); //TODO write to fpga regs?
- //rx_set_atr_txval(io_rx_while_tx);
- //tx_set_atr_rxval(io_tx_while_rx);
- //tx_set_atr_txval(io_tx_while_tx);
-
- printf("GPIO: RXRX=%04X RXTX=%04X TXRX=%04X TXTX=%04X\n",
- io_rx_while_rx, io_rx_while_tx, io_tx_while_rx, io_tx_while_tx);
+ /* FIXME better way to set rx and tx val for RX and TX banks */
+ /* set rx bank */
+ db->base.atr_rxval = EN|rx_hp|RX_EN;
+ db->base.atr_txval = EN|rx_hp;
+ set_atr_regs(GPIO_RX_BANK, (struct db_base *)db);
+ /* set tx bank */
+ db->base.atr_rxval = HB_PA_OFF|LB_PA_OFF|rx_antsel|ad9515_sel;
+ db->base.atr_txval = tx_pa_sel|tx_antsel|tx_enb_sel|ad9515_sel;
+ set_atr_regs(GPIO_TX_BANK, (struct db_base *)db);
}
/**************************************************
- * Read register
- **************************************************/
-int
-rx_read_io(){
- //int val;
- //if(d_which)
- // val = FR_RB_IO_RX_B_IO_TX_B;
- //else
- // val = FR_RB_IO_RX_A_IO_TX_A;
- int t = 0;//usrp()->_read_fpga_reg(val);
- return (t >> 16) & 0xffff;
-}
-
-/**************************************************
* Init for TX and RX
**************************************************/
bool
xcvr2450_init(struct db_base *dbb){
struct db_xcvr2450_dummy *db = (struct db_xcvr2450_dummy *) dbb;
- // Sane defaults
- db->common.d_mimo = 1; // 0 = OFF, 1 = ON
- db->common.d_int_div = 192; // 128 = min, 255 = max
- db->common.d_frac_div = 0; // 0 = min, 65535 = max
- db->common.d_highband = 0; // 0 = freq <= 5.4e9, 1 = freq > 5.4e9
- db->common.d_five_gig = 0; // 0 = freq <= 3.e9, 1 = freq > 3e9
- db->common.d_cp_current = 0; // 0 = 2mA, 1 = 4mA
- db->common.d_ref_div = 4; // 1 to 7
- db->common.d_rssi_hbw = 0; // 0 = 2 MHz, 1 = 6 MHz
- db->common.d_txlpf_bw = 1; // 1 = 12 MHz, 2 = 18 MHz, 3 = 24 MHz
- db->common.d_rxlpf_bw = 1; // 0 = 7.5 MHz, 1 = 9.5 MHz, 2 = 14 MHz, 3 =
18 MHz
- db->common.d_rxlpf_fine = 2; // 0 = 90%, 1 = 95%, 2 = 100%, 3 = 105%, 4 =
110%
- db->common.d_rxvga_ser = 1; // 0 = RXVGA controlled by B7:1,
1=controlled serially
- db->common.d_rssi_range = 1; // 0 = low range (datasheet typo), 1=high
range (0.5V - 2.0V)
- db->common.d_rssi_mode = 1; // 0 = enable follows RXHP, 1 = enabled
- db->common.d_rssi_mux = 0; // 0 = RSSI, 1 = TEMP
- db->common.d_rx_hp_pin = 0; // 0 = Fc set by rx_hpf, 1 = 600 KHz
- db->common.d_rx_hpf = 0; // 0 = 100Hz, 1 = 30KHz
- db->common.d_rx_ant = 0; // 0 = Ant. #1, 1 = Ant. #2
- db->common.d_tx_ant = 0; // 0 = Ant. #1, 1 = Ant. #2
- db->common.d_txvga_ser = 1; // 0 = TXVGA controlled by B6:1,
1=controlled serially
- db->common.d_tx_driver_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%,
3=100% (best lin)
- db->common.d_tx_vga_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%,
3=100% (best lin)
- db->common.d_tx_upconv_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%,
3=100% (best lin)
- db->common.d_tx_bb_gain = 3; // 0=maxgain-5dB, 1=max-3dB, 2=max-1.5dB,
3=max
- db->common.d_pabias_delay = 15; // 0 = 0, 15 = 7uS
- db->common.d_pabias = 0; // 0 = 0 uA, 63 = 315uA
- db->common.d_rx_rf_gain = 0; // 0 = 0dB, 1 = 0dB, 2 = 15dB, 3 = 30dB
- db->common.d_rx_bb_gain = 16; // 0 = min, 31 = max (0 - 62 dB)
- db->common.d_txgain = 63; // 0 = min, 63 = max
-
- /*
- // Initialize GPIO and ATR
- tx_write_io(TX_SAFE_IO, TX_OE_MASK);
- tx_write_oe(TX_OE_MASK, ~0);
- tx_set_atr_txval(TX_SAFE_IO);
- tx_set_atr_rxval(TX_SAFE_IO);
- tx_set_atr_mask(TX_OE_MASK);
-
- rx_write_io(RX_SAFE_IO, RX_OE_MASK);
- rx_write_oe(RX_OE_MASK, ~0);
- rx_set_atr_rxval(RX_SAFE_IO);
- rx_set_atr_txval(RX_SAFE_IO);
- rx_set_atr_mask(RX_OE_MASK);
- */
- // Initialize chipset
- // TODO: perform reset sequence to ensure power up defaults
+ /* Initialize chipset */
+ clocks_enable_tx_dboard(true, MASTER_REF_CLK_DIV);
+ set_gpio(db);
set_reg_standby(db);
set_reg_bandselpll(db);
set_reg_cal(db);
@@ -374,26 +343,23 @@
set_reg_pabias(db);
set_reg_rxgain(db);
set_reg_txgain(db);
- //FIXME: set_freq(2.45e9);
-
- db->base.set_gain(dbb, (db->base.gain_max - db->base.gain_min)/2); //set
mid-range gain
+ //u2_fxpt_freq_t dc;
+ //db->base.set_freq(dbb, U2_DOUBLE_TO_FXPT_FREQ(2.434e9), &dc);
return true;
}
/**************************************************
* Lock detect
**************************************************/
-bool
+static bool
lock_detect(){
- /*
- @returns: the value of the VCO/PLL lock detect bit.
- @rtype: 0 or 1
- */
- if(rx_read_io() & LOCKDET) {
+ //true when the VCO/PLL lock detect bit is set.
+ if(hal_gpio_read(GPIO_RX_BANK) & LOCKDET) {
return true;
}
else { // Give it a second chance
- if(rx_read_io() & LOCKDET)
+ mdelay(1);
+ if(hal_gpio_read(GPIO_RX_BANK) & LOCKDET)
return true;
else
return false;
@@ -405,78 +371,67 @@
**************************************************/
bool
xcvr2450_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t
*dc){
+ unsigned int scaler, div_factor, actual_div_q16;
struct db_xcvr2450_dummy *db = (struct db_xcvr2450_dummy *) dbb;
- //ensure gain in within range
- if(!(freq >= db->base.freq_min && freq <= db->base.freq_max)) {
+ /* determine if the freq range is in low or high band */
+ if (freq >= LB_FREQ_MIN && freq <= LB_FREQ_MAX) {
+ db->common->d_five_gig = 0;
+ scaler = 3;
+ //printf("2.4-GHZ\n");
+ } else if (freq >= HB_FREQ_MIN && freq <= HB_FREQ_MAX) {
+ db->common->d_five_gig = 1;
+ scaler = 5;
+ //printf("5-GHZ\n");
+ } else {
+ printf("Out of range\n");
return false;
}
-
-
- u2_fxpt_freq_t vco_freq;
-
- if(freq > U2_DOUBLE_TO_FXPT_FREQ(3e9)) {
- db->common.d_five_gig = 1;
- db->common.d_ref_div = 1;
- db->common.d_ad9515_div = 3;
- //scaler = U2_DOUBLE_TO_FXPT_FREQ(4.0/5.0);
- vco_freq = (4*freq)/5;
+ /* set the highband bit */
+ if(freq > U2_DOUBLE_TO_FXPT_FREQ(5.408e9)) {
+ db->common->d_highband = 1;
+ //printf("5-HB\n");
}
else {
- db->common.d_five_gig = 0;
- db->common.d_ref_div = 1;
- db->common.d_ad9515_div = 3;
- //scaler = U2_DOUBLE_TO_FXPT_FREQ(4.0/3.0);
- vco_freq = (4*freq)/3;
+ db->common->d_highband = 0;
+ //printf("5-LB\n");
}
-
- if(freq > U2_DOUBLE_TO_FXPT_FREQ(5.27e9)) {
- db->common.d_highband = 1;
- }
- else {
- db->common.d_highband = 0;
- }
-
- //double vco_freq = target_freq*scaler;
- //double sys_clk = usrp()->fpga_master_clock_freq(); // Usually 64e6
- u2_fxpt_freq_t ref_clk =
U2_DOUBLE_TO_FXPT_FREQ(MASTER_CLK_RATE)/db->common.d_ad9515_div;
- u2_fxpt_freq_t phdet_freq = ref_clk/db->common.d_ref_div;
-
- //double div = vco_freq/phdet_freq;
- // d_int_div = int(floor(div));
- // d_frac_div = int((div-d_int_div)*65536.0);
- // double actual_freq = phdet_freq*(d_int_div+(d_frac_div/65536.0))/scaler;
- db->common.d_int_div = vco_freq/phdet_freq;
- *dc = db->common.d_int_div*phdet_freq*freq/vco_freq;
-
-
- printf("RF=%d VCO=%d RefDiv=%d Phdet=%d Div=%d ActualRF=%d\n",
- u2_fxpt_freq_round_to_int(freq), u2_fxpt_freq_round_to_int(vco_freq),
- db->common.d_ref_div, u2_fxpt_freq_round_to_int(phdet_freq),
- db->common.d_int_div, u2_fxpt_freq_round_to_int(*dc));
-
+ unsigned int loop_iter = 0;
+ do { /* set the dividers so that the n divider is above the practical
minimum */
+ switch(loop_iter){
+ case 0:
+ db->common->d_ad9515_div = 3;
+ db->common->d_ref_div = 1;
+ break;
+ case 1:
+ db->common->d_ad9515_div = 2;
+ db->common->d_ref_div = 2;
+ break;
+ default:
+ db->common->d_ad9515_div = 3;
+ db->common->d_ref_div = loop_iter;
+ }
+ loop_iter++;
+ div_factor =
db->common->d_ref_div*db->common->d_ad9515_div*4*MASTER_REF_CLK_DIV;
+ actual_div_q16 = ((freq*div_factor)/(scaler*MASTER_CLK_RATE)) >>
(U2_FPF_RP-16);
+ } while (actual_div_q16 < N_DIV_MIN_Q16);
+ /* calculate the divisors */
+ db->common->d_int_div = actual_div_q16 >> 16;
+ db->common->d_frac_div = actual_div_q16 & 0xffff; //isolate lower 16 bits
+ /* calculate the dc freq */
+ *dc = ((((u2_fxpt_freq_t)MASTER_CLK_RATE)*actual_div_q16*scaler) /
div_factor) << (U2_FPF_RP-16);
+ /*printf("scaler %d, div(int) %u, div_factor %d, ad9515_div %u, ref_div
%u\n",
+ scaler, db->common->d_int_div, div_factor, db->common->d_ad9515_div,
db->common->d_ref_div);
+ printf("actual div %u, Target Freq %uKHz, Actual Freq %uKHz\n",
+ actual_div_q16, u2_fxpt_freq_round_to_int(freq/1000),
u2_fxpt_freq_round_to_int(*dc/1000));
+ */
set_gpio(db);
set_reg_int_divider(db);
set_reg_frac_divider(db);
set_reg_bandselpll(db);
bool ok = lock_detect();
-
- if(ok) {
- if((freq > U2_DOUBLE_TO_FXPT_FREQ(5.275e9)) && (freq <=
U2_DOUBLE_TO_FXPT_FREQ(5.35e9))) {
- db->common.d_highband = 0;
- set_reg_bandselpll(db);
- ok = lock_detect();
- printf("swap to 0 at %d, ok %d\n", u2_fxpt_freq_round_to_int(freq), ok);
- }
- if((freq >= U2_DOUBLE_TO_FXPT_FREQ(5.25e9)) && (freq <=
U2_DOUBLE_TO_FXPT_FREQ(5.275e9))) {
- db->common.d_highband = 1;
- set_reg_bandselpll(db);
- ok = lock_detect();
- printf("swap to 1 at %d, ok %d\n", u2_fxpt_freq_round_to_int(freq), ok);
- }
- if(!ok){
- printf("Fail %d\n", u2_fxpt_freq_round_to_int(freq));
- }
+ if(!ok){
+ printf("Fail lock detect %uKHz\n", u2_fxpt_freq_round_to_int(freq/1000));
}
return ok;
}
@@ -487,24 +442,25 @@
bool
xcvr2450_set_gain_rx(struct db_base *dbb, u2_fxpt_gain_t gain){
struct db_xcvr2450_dummy *db = (struct db_xcvr2450_dummy *) dbb;
- //ensure gain in within range
+ //ensure gain is within range
if(!(gain >= db->base.gain_min && gain <= db->base.gain_max)) {
return false;
}
// Split the gain between RF and baseband
// This is experimental, not prescribed
if(gain < U2_DOUBLE_TO_FXPT_GAIN(30.0)) {
- db->common.d_rx_rf_gain = 0; // 0 dB RF gain
- db->common.d_rx_bb_gain = gain/U2_DOUBLE_TO_FXPT_GAIN(2.0);
+ db->common->d_rx_rf_gain = 0; // 0 dB RF gain
+ db->common->d_rx_bb_gain = u2_fxpt_gain_round_to_int(gain/2);
}
else if(gain >= U2_DOUBLE_TO_FXPT_GAIN(30.0) && gain <
U2_DOUBLE_TO_FXPT_GAIN(61.0)) {
- db->common.d_rx_rf_gain = 2; // 15 dB RF gain
- db->common.d_rx_bb_gain =
(gain-U2_DOUBLE_TO_FXPT_GAIN(15.0))/U2_DOUBLE_TO_FXPT_GAIN(2.0);
+ db->common->d_rx_rf_gain = 2; // 15 dB RF gain
+ db->common->d_rx_bb_gain =
u2_fxpt_gain_round_to_int((gain-U2_DOUBLE_TO_FXPT_GAIN(15.0))/2);
}
else if(gain >= U2_DOUBLE_TO_FXPT_GAIN(61.0)) {
- db->common.d_rx_rf_gain = 3; // 30.5 dB RF gain
- db->common.d_rx_bb_gain =
(gain-U2_DOUBLE_TO_FXPT_GAIN(30.5))/U2_DOUBLE_TO_FXPT_GAIN(2.0);
+ db->common->d_rx_rf_gain = 3; // 30.5 dB RF gain
+ db->common->d_rx_bb_gain =
u2_fxpt_gain_round_to_int((gain-U2_DOUBLE_TO_FXPT_GAIN(30.5))/2);
}
+ //printf("RX RF Gain %u, RX BB Gain %u\n", db->common->d_rx_rf_gain,
db->common->d_rx_bb_gain);
set_reg_rxgain(db);
return true;
}
@@ -520,12 +476,18 @@
return false;
}
//scale for register and set
- db->common.d_txgain = gain/db->base.gain_step_size;
+ db->common->d_txgain = (gain*63)/db->base.gain_max;
+ //printf("TX Gain %u, TX Reg %u\n", u2_fxpt_gain_round_to_int(gain),
db->common->d_txgain);
set_reg_txgain(db);
return true;
}
+/**************************************************
+ * Set TX Enable
+ **************************************************/
bool
-xcvr2450_set_tx_enable(struct db_base *db, bool on){
+xcvr2450_set_tx_enable(struct db_base *dbb, bool on){
+ struct db_xcvr2450_dummy *db = (struct db_xcvr2450_dummy *) dbb;
+ db->common->d_tx_enb = on;
return true;
}
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- [Commit-gnuradio] r10405 - gnuradio/branches/releases/3.2/usrp2/firmware/lib,
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