[Commit-gnuradio] r10397 - gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib

[pcreekmore]

Author: pcreekmore
Date: 2009-02-05 14:04:05 -0700 (Thu, 05 Feb 2009)
New Revision: 10397

Modified:
   
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
Log:
Validated version of FGPA configuration with 16, 8, 4, 2, and 1-bit 
quantization options.

Modified: 
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
===================================================================
--- 
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
  2009-02-05 18:00:10 UTC (rev 10396)
+++ 
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
  2009-02-05 21:04:05 UTC (rev 10397)
@@ -84,12 +84,13 @@
    
    // FIFO
    wire          ch0_in, ch0_out, iq_out;
-   assign        ch0_in = (write_phase == 1);
+   assign        ch0_in = (write_phase == 1 && read_phase_delayed == 1);
 
    fifo_4k_18 rxfifo 
      ( // DSP Write Side
-       .data ( {ch0_in, write_phase[0], fifodata} ),
-       .wrreq (~rx_full & (write_phase != 0)),
+       .data ( {ch0_in, ch0_in, fifodata} ),
+       //.data ( {ch0_in, write_phase[0], fifodata} ),
+       .wrreq (write_phase != 0),
        .wrclk ( rxclk ),
        .wrfull ( rx_full ),
        .wrempty ( ),
@@ -118,10 +119,22 @@
    reg [15:0] ch_6_buff0, ch_6_buff1;
    reg [15:0] ch_7_buff0, ch_7_buff1;
 
+   // Counter for validation purposes
+//   reg [15:0] counter;
+//   always @(posedge rxclk)
+//     if (reset)
+//       counter <= 16'b0;
+//     else if (rxstrobe)
+//       counter <= counter + 16'd1;
+//     else
+//       counter <= counter;
+     
+
    // Input buffers
    always @(posedge rxclk)
      if (rxstrobe)
        begin
+         //ch_0_buff0 <= 16'd0;
          ch_0_buff0 <= ch_0;
          ch_0_buff1 <= ch_0_buff0;
          ch_0_buff2 <= ch_0_buff1;
@@ -131,6 +144,7 @@
          ch_0_buff6 <= ch_0_buff5;
          ch_0_buff7 <= ch_0_buff6;
 
+         //ch_1_buff0 <= 16'd1;
          ch_1_buff0 <= ch_1;
          ch_1_buff1 <= ch_1_buff0;
          ch_1_buff2 <= ch_1_buff1;
@@ -140,35 +154,41 @@
          ch_1_buff6 <= ch_1_buff5;
          ch_1_buff7 <= ch_1_buff6;
 
+         //ch_2_buff0 <= 16'd2;
          ch_2_buff0 <= ch_2;
          ch_2_buff1 <= ch_2_buff0;
          ch_2_buff2 <= ch_2_buff1;
          ch_2_buff3 <= ch_2_buff2;
 
+         //ch_3_buff0 <= 16'd3;
          ch_3_buff0 <= ch_3;
          ch_3_buff1 <= ch_3_buff0;
          ch_3_buff2 <= ch_3_buff1;
          ch_3_buff3 <= ch_3_buff2;
 
-         ch_4_buff0 <= 16'h10; //ch_4;
+         //ch_4_buff0 <= 16'd4;
+         ch_4_buff0 <= ch_4;
          ch_4_buff1 <= ch_4_buff0;
          ch_4_buff2 <= ch_4_buff1;
          ch_4_buff3 <= ch_4_buff2;
 
-         ch_5_buff0 <= 16'h10; //ch_5;
+         //ch_5_buff0 <= 16'd5;
+         ch_5_buff0 <= ch_5;
          ch_5_buff1 <= ch_5_buff0;
          ch_5_buff2 <= ch_5_buff1;
          ch_5_buff3 <= ch_5_buff2;
 
-         ch_6_buff0 <= 16'h10; //ch_6;
+         //ch_6_buff0 <= 16'd6;
+         ch_6_buff0 <= ch_6;
          ch_6_buff1 <= ch_6_buff0;
          
-         ch_7_buff0 <= 16'h10; //ch_7;
+         //ch_7_buff0 <= 16'd7;
+         ch_7_buff0 <= ch_7;
          ch_7_buff1 <= ch_7_buff0;
        end
 
 
-   // buffer store event counter and pulse
+   // buffer store event counter
    reg [3:0] buffstore_count;
    always @(posedge rxclk)
      if (reset)
@@ -247,18 +267,24 @@
 
 
    // "read phase" counter to keep track of 6-channel cases
-   // Note: could easily change this to only increment for the 6-channel case 
if necessary
    reg [1:0] read_phase;
+   reg [1:0] read_phase_delayed;
    always @(posedge rxclk)
      if (reset)
-       read_phase <= 2'd1;
-     else if (buffs_ready)
-       case(bitwidth)
-         5'd4 : if (read_phase == 2'd2) read_phase <= 2'd1; else read_phase <= 
read_phase+2'd1;
-         5'd2 : if (read_phase == 2'd3) read_phase <= 2'd1; else read_phase <= 
read_phase+2'd1;
-         5'd1 : if (read_phase == 2'd3) read_phase <= 2'd1; else read_phase <= 
read_phase+2'd1;
-         default : read_phase <= 2'd1;
-       endcase
+       begin
+         read_phase <= 2'd1;
+         read_phase_delayed <= 2'd0;
+       end
+     else if (channels == 4'd6 && buffs_ready)
+       begin
+         read_phase_delayed <= read_phase;
+         case(bitwidth)
+           5'd4 : if (read_phase == 2'd2) read_phase <= 2'd1; else read_phase 
<= read_phase+2'd1;
+           5'd2 : if (read_phase == 2'd3) read_phase <= 2'd1; else read_phase 
<= read_phase+2'd1;
+           5'd1 : if (read_phase == 2'd3) read_phase <= 2'd1; else read_phase 
<= read_phase+2'd1;
+           default : read_phase <= 2'd1;
+         endcase
+       end
      else
        read_phase <= read_phase;
 
@@ -368,7 +394,7 @@
 
    // total number of writes per read phase
    reg [3:0] total_writes;
-   always @(bitwidth or channels or read_phase)
+   always @(bitwidth or channels or read_phase_delayed)
      if (bitwidth == 5'd2 || bitwidth == 5'd1)
        total_writes <= 1;
      else
@@ -378,7 +404,7 @@
              4'd2 : total_writes <= 4'd1;
              4'd4 : total_writes <= 4'd1;
              4'd6 :
-               case(read_phase)
+               case(read_phase_delayed)
                  2'd1 : total_writes <= 4'd1;
                  2'd2 : total_writes <= 4'd2;
                  default : total_writes <= 4'b0;
@@ -442,23 +468,26 @@
    // Rounding (Quantization) functions
    function [7:0] round_8;
       input [15:0] in_val;
-      
-      round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
+      //round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
+      round_8 = in_val[7:0];
    endfunction // round_8
 
    function [3:0] round_4;
      input [15:0] in_val;
-     round_4 = in_val[15:12] + (in_val[15] & |in_val[11:0]);
+     //round_4 = in_val[15:12] + (in_val[15] & |in_val[11:0]);
+     round_4 = in_val[3:0];
    endfunction // round_4
 
    function [1:0] round_2;
      input [15:0] in_val;
-     round_2 = in_val[15:14] + (in_val[15] & |in_val[13:0]);
+     //round_2 = in_val[15:14] + (in_val[15] & |in_val[13:0]);
+     round_2 = in_val[1:0];
    endfunction // round_2
 
    function [0:0] round_1;
      input [15:0] in_val;
-     round_1 = ~in_val[15];
+     //round_1 = ~in_val[15];
+     round_1 = in_val[0];
    endfunction // round_1
       
 
@@ -473,7 +502,7 @@
    always @(posedge rxclk)
      if(reset)
        rx_overrun_dsp <= 1'b0;
-     else if(buffs_ready && write_phase != 4'b0 && write_phase != total_writes)
+     else if((buffs_ready && write_phase != 4'b0 && write_phase != 
total_writes) || (write_phase != 4'b0 && rx_full))
        rx_overrun_dsp <= 1'b1;
      else if(clear_status_dsp)
        rx_overrun_dsp <= 1'b0;