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[Commit-gnuradio] r10307 - gnuradio/branches/developers/pcreekmore/quant
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From: |
pcreekmore |
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Subject: |
[Commit-gnuradio] r10307 - gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib |
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Date: |
Mon, 26 Jan 2009 23:49:24 -0700 (MST) |
Author: pcreekmore
Date: 2009-01-26 23:49:22 -0700 (Mon, 26 Jan 2009)
New Revision: 10307
Modified:
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
Log:
Full support for 16, 8, 4, 2, and 1-bit quantization with 2, 4, 6, or 8
channels; NOT validated.
Modified:
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
===================================================================
---
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
2009-01-26 22:07:51 UTC (rev 10306)
+++
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
2009-01-27 06:49:22 UTC (rev 10307)
@@ -53,8 +53,7 @@
output [31:0] debugbus
);
- wire [15:0] fifodata, fifodata_8_old;
- reg [15:0] fifodata_16;
+ reg [15:0] fifodata;
wire [11:0] rxfifolevel;
wire rx_full;
@@ -85,12 +84,12 @@
// FIFO
wire ch0_in, ch0_out, iq_out;
- assign ch0_in = (phase == 1);
+ assign ch0_in = (write_phase == 1);
fifo_4k_18 rxfifo
( // DSP Write Side
- .data ( {ch0_in, phase[0], fifodata} ),
- .wrreq (~rx_full & (phase != 0)),
+ .data ( {ch0_in, write_phase[0], fifodata} ),
+ .wrreq (~rx_full & (write_phase != 0)),
.wrclk ( rxclk ),
.wrfull ( rx_full ),
.wrempty ( ),
@@ -151,24 +150,25 @@
ch_3_buff2 <= ch_3_buff1;
ch_3_buff3 <= ch_3_buff2;
- ch_4_buff0 <= ch_4;
+ ch_4_buff0 <= 16'h10; //ch_4;
ch_4_buff1 <= ch_4_buff0;
ch_4_buff2 <= ch_4_buff1;
ch_4_buff3 <= ch_4_buff2;
- ch_5_buff0 <= ch_5;
+ ch_5_buff0 <= 16'h10; //ch_5;
ch_5_buff1 <= ch_5_buff0;
ch_5_buff2 <= ch_5_buff1;
ch_5_buff3 <= ch_5_buff2;
- ch_6_buff0 <= ch_6;
+ ch_6_buff0 <= 16'h10; //ch_6;
ch_6_buff1 <= ch_6_buff0;
- ch_7_buff0 <= ch_7;
+ ch_7_buff0 <= 16'h10; //ch_7;
ch_7_buff1 <= ch_7_buff0;
end
- // buffer store event counter
+
+ // buffer store event counter and pulse
reg [3:0] buffstore_count;
always @(posedge rxclk)
if (reset)
@@ -178,181 +178,192 @@
buffstore_count <= 4'd1;
else
buffstore_count <= buffstore_count + 4'd1;
+ else if (buffs_ready)
+ buffstore_count <= 4'b0;
else
buffstore_count <= buffstore_count;
- // Logic to determine if a sufficient number of new samples has been read
- // into the buffers in order to write a full 16-bit word to the output fifo
- reg buffs_ready;
- always @*
- if (bitwidth == 5'd16 || bitwidth == 5'd8 && buffstore_count == 4'd1)
- buffs_ready <= 1;
- else if (channels == 4'd2)
- case(bitwidth)
- 5'd4 : if (buffstore_count == 4'd2) buffs_ready <= 1; else
buffs_ready <= 0;
- 5'd2 : if (buffstore_count == 4'd4) buffs_ready <= 1; else
buffs_ready <= 0;
- 5'd1 : if (buffstore_count == 4'd8) buffs_ready <= 1; else
buffs_ready <= 0;
- default : buffs_ready <= 0;
- endcase
- else if (channels == 4'd4)
- case(bitwidth)
- 5'd4 : if (buffstore_count == 4'd1) buffs_ready <= 1; else
buffs_ready <= 0;
- 5'd2 : if (buffstore_count == 4'd2) buffs_ready <= 1; else
buffs_ready <= 0;
- 5'd1 : if (buffstore_count == 4'd4) buffs_ready <= 1; else
buffs_ready <= 0;
- default : buffs_ready <= 0;
- endcase
- else if (channels == 4'd6)
- case(bitwidth)
- 5'd4 : if (buffstore_count == 4'd1) buffs_ready <= 1; else
buffs_ready <= 0;
- 5'd2 :
- case(read_phase)
- 2'd1 : if (buffstore_count == 4'd2) buffs_ready <= 1; else
buffs_ready <= 0;
- 2'd2 : if (buffstore_count == 4'd1) buffs_ready <= 1; else
buffs_ready <= 0;
- 2'd3 : if (buffstore_count == 4'd1) buffs_ready <= 1; else
buffs_ready <= 0;
- default : buffs_ready <= 0;
+ // the total number of buffer stores required before writing to fifo
+ reg [3:0] total_stores;
+ always @(bitwidth or channels or read_phase)
+ if (bitwidth == 5'd16 || bitwidth == 5'd8) total_stores <= 4'd1;
+ else
+ case(channels)
+ 4'd2 :
+ case(bitwidth)
+ 5'd4 : total_stores <= 4'd2;
+ 5'd2 : total_stores <= 4'd4;
+ 5'd1 : total_stores <= 4'd8;
+ default : total_stores <= 4'd1;
endcase
- 5'd1 :
- case(read_phase)
- 2'd1 : if (buffstore_count == 4'd3) buffs_ready <= 1; else
buffs_ready <= 0;
- 2'd2 : if (buffstore_count == 4'd3) buffs_ready <= 1; else
buffs_ready <= 0;
- 2'd3 : if (buffstore_count == 4'd2) buffs_ready <= 1; else
buffs_ready <= 0;
- default : buffs_ready <= 0;
+ 4'd4 :
+ case(bitwidth)
+ 5'd4 : total_stores <= 4'd1;
+ 5'd2 : total_stores <= 4'd2;
+ 5'd1 : total_stores <= 4'd4;
+ default : total_stores <= 4'd1;
endcase
- default : buffs_ready <= 0;
+ 4'd6 :
+ case(bitwidth)
+ 5'd4 : total_stores <= 4'd1;
+ 5'd2 :
+ case(read_phase)
+ 2'd1 : total_stores <= 4'd2;
+ 2'd2 : total_stores <= 4'd1;
+ 2'd3 : total_stores <= 4'd1;
+ default : total_stores <= 4'd1;
+ endcase
+ 5'd1 :
+ case(read_phase)
+ 2'd1 : total_stores <= 4'd3;
+ 2'd2 : total_stores <= 4'd3;
+ 2'd3 : total_stores <= 4'd2;
+ default : total_stores <= 4'd1;
+ endcase
+ default total_stores <= 4'd1;
+ endcase
+ 4'd8 :
+ case(bitwidth)
+ 5'd4 : total_stores <= 4'd1;
+ 5'd2 : total_stores <= 4'd1;
+ 5'd1 : total_stores <= 4'd2;
+ default : total_stores <= 4'd1;
+ endcase
+ default : total_stores <= 4'd1;
endcase
- else if (channels == 4'd8)
- case(bitwidth)
- 5'd4 : if (buffstore_count == 4'd1) buffs_ready <= 1; else
buffs_ready <= 0;
- 5'd2 : if (buffstore_count == 4'd1) buffs_ready <= 1; else
buffs_ready <= 0;
- 5'd1 : if (buffstore_count == 4'd2) buffs_ready <= 1; else
buffs_ready <= 0;
- default : buffs_ready <= 0;
- endcase
- else
- buffs_ready <= 0;
- // write strobe; begins fifo write for a single read phase
- reg write_strobe;
- always @(posedge buffs_ready)
- write_strobe <= 1;
- always @(posedge rxclk)
- write_strobe <= 0;
+ // Logic to determine if a sufficient number of new samples has been read
+ // into the buffers in order to write a full 16-bit word to the output fifo
+ wire buffs_ready;
+ assign buffs_ready = (buffstore_count == total_stores);
+
+// always @(buffstore_count)
+// if (reset)
+// buffs_ready <= 0;
+// else
+// buffs_ready <= (buffstore_count == total_stores);
+
+
// "read phase" counter to keep track of 6-channel cases
// Note: could easily change this to only increment for the 6-channel case
if necessary
reg [1:0] read_phase;
- always @(posedge buffs_ready)
+ always @(posedge rxclk)
if (reset)
- read_phase <= 2'd0;
- else
+ read_phase <= 2'd1;
+ else if (buffs_ready)
case(bitwidth)
5'd4 : if (read_phase == 2'd2) read_phase <= 2'd1; else read_phase <=
read_phase+2'd1;
5'd2 : if (read_phase == 2'd3) read_phase <= 2'd1; else read_phase <=
read_phase+2'd1;
5'd1 : if (read_phase == 2'd3) read_phase <= 2'd1; else read_phase <=
read_phase+2'd1;
default : read_phase <= 2'd1;
endcase
+ else
+ read_phase <= read_phase;
// Buffer output assignments, based on number of channels and sample width
(bitwidth)
reg [15:0] fifodata_1, fifodata_2, fifodata_3, fifodata_4, fifodata_5,
fifodata_6, fifodata_7, fifodata_8;
- always @(posedge write_strobe)
+ always @(posedge rxclk)
begin
- if (bitwidth == 5'd16)
- begin
- fifodata_1 <= ch_0_buff0;
- fifodata_2 <= ch_1_buff0;
- fifodata_3 <= ch_2_buff0;
- fifodata_4 <= ch_3_buff0;
- fifodata_5 <= ch_4_buff0;
- fifodata_6 <= ch_5_buff0;
- fifodata_7 <= ch_6_buff0;
- fifodata_8 <= ch_7_buff0;
- end
- else if (bitwidth == 5'd8)
- begin
- fifodata_1 <= {round_8(ch_1_buff0),round_8(ch_0_buff0)};
- fifodata_2 <= {round_8(ch_3_buff0),round_8(ch_2_buff0)};
- fifodata_3 <= {round_8(ch_5_buff0),round_8(ch_4_buff0)};
- fifodata_4 <= {round_8(ch_7_buff0),round_8(ch_6_buff0)};
- end
- else
- case(channels)
- 4'd2 :
- case(bitwidth)
- 5'd4 : fifodata_1 <=
{round_4(ch_1_buff0),round_4(ch_0_buff0),round_4(ch_1_buff1),round_4(ch_0_buff1)};
- 5'd2 : fifodata_1 <=
{round_2(ch_1_buff0),round_2(ch_0_buff0),round_2(ch_1_buff1),round_2(ch_0_buff1),
-
round_2(ch_1_buff2),round_2(ch_0_buff2),round_2(ch_1_buff3),round_2(ch_0_buff3)};
- 5'd1 : fifodata_1 <=
{round_1(ch_1_buff0),round_1(ch_0_buff0),round_1(ch_1_buff1),round_1(ch_0_buff1),
-
round_1(ch_1_buff2),round_1(ch_0_buff2),round_1(ch_1_buff3),round_1(ch_0_buff3),
-
round_1(ch_1_buff4),round_1(ch_0_buff4),round_1(ch_1_buff5),round_1(ch_0_buff5),
-
round_1(ch_1_buff6),round_1(ch_0_buff6),round_1(ch_1_buff7),round_1(ch_0_buff7)};
- default: fifodata_1 <= 16'b0;
- endcase
- 4'd4 :
- case(bitwidth)
- 5'd4 : fifodata_1 <=
{round_4(ch_3_buff0),round_4(ch_2_buff0),round_4(ch_1_buff0),round_4(ch_0_buff0)};
- 5'd2 : fifodata_1 <=
{round_2(ch_3_buff0),round_2(ch_2_buff0),round_2(ch_1_buff0),round_2(ch_0_buff0),
-
round_2(ch_3_buff1),round_2(ch_2_buff1),round_2(ch_1_buff1),round_2(ch_0_buff1)};
- 5'd1 : fifodata_1 <=
{round_1(ch_3_buff0),round_1(ch_2_buff0),round_1(ch_1_buff0),round_1(ch_0_buff0),
-
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1),
-
round_1(ch_3_buff2),round_1(ch_2_buff2),round_1(ch_1_buff2),round_1(ch_0_buff2),
-
round_1(ch_3_buff3),round_1(ch_2_buff3),round_1(ch_1_buff3),round_1(ch_0_buff3)};
- default : fifodata_1 <= 16'b0;
- endcase
- 4'd6 :
- case(bitwidth)
- 5'd4 :
- case(read_phase)
- 2'd1 : fifodata_1 <=
{round_4(ch_3_buff0),round_4(ch_2_buff0),round_4(ch_1_buff0),round_4(ch_0_buff0)};
- 2'd2 : begin
- fifodata_1 <=
{round_4(ch_1_buff0),round_4(ch_0_buff0),round_4(ch_5_buff1),round_4(ch_4_buff1)};
- fifodata_2 <=
{round_4(ch_5_buff0),round_4(ch_4_buff0),round_4(ch_3_buff0),round_4(ch_2_buff0)};
- end
- default : fifodata_1 <= 16'b0;
- endcase
- 5'd2 :
- case(read_phase)
- 2'd1 : fifodata_1 <=
{round_2(ch_1_buff0),round_2(ch_0_buff0),round_2(ch_5_buff1),round_2(ch_4_buff1),
-
round_2(ch_3_buff1),round_2(ch_2_buff1),round_2(ch_1_buff1),round_2(ch_0_buff1)};
- 2'd2 : fifodata_1 <=
{round_2(ch_3_buff0),round_2(ch_2_buff0),round_2(ch_1_buff0),round_2(ch_0_buff0),
-
round_2(ch_5_buff1),round_2(ch_4_buff1),round_2(ch_3_buff1),round_2(ch_2_buff1)};
- 2'd3 : fifodata_1 <=
{round_2(ch_5_buff0),round_2(ch_4_buff0),round_2(ch_3_buff0),round_2(ch_2_buff0),
-
round_2(ch_1_buff0),round_2(ch_0_buff0),round_2(ch_5_buff1),round_2(ch_4_buff1)};
- default : fifodata_1 <= 16'b0;
- endcase
- 5'd1 :
- case(read_phase)
- 2'd1 : fifodata_1 <=
{round_1(ch_3_buff0),round_1(ch_2_buff0),round_1(ch_1_buff0),round_1(ch_0_buff0),
-
round_1(ch_5_buff1),round_1(ch_4_buff1),round_1(ch_3_buff1),round_1(ch_2_buff1),
-
round_1(ch_1_buff1),round_1(ch_0_buff1),round_1(ch_5_buff2),round_1(ch_4_buff2),
-
round_1(ch_3_buff2),round_1(ch_2_buff2),round_1(ch_1_buff2),round_1(ch_0_buff2)};
- 2'd2 : fifodata_1 <=
{round_1(ch_1_buff0),round_1(ch_0_buff0),round_1(ch_5_buff1),round_1(ch_4_buff1),
-
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1),
-
round_1(ch_5_buff2),round_1(ch_4_buff2),round_1(ch_3_buff2),round_1(ch_2_buff2),
-
round_1(ch_1_buff2),round_1(ch_0_buff2),round_1(ch_5_buff3),round_1(ch_4_buff3)};
- 2'd3 : fifodata_1 <=
{round_1(ch_5_buff0),round_1(ch_4_buff0),round_1(ch_3_buff0),round_1(ch_2_buff0),
-
round_1(ch_1_buff0),round_1(ch_0_buff0),round_1(ch_5_buff1),round_1(ch_4_buff1),
-
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1),
-
round_1(ch_5_buff2),round_1(ch_4_buff2),round_1(ch_3_buff2),round_1(ch_2_buff2)};
- default : fifodata_1 <= 16'b0;
- endcase
- default : fifodata_1 <= 16'b0;
- endcase
- 4'd8 :
- case(bitwidth)
- 5'd4 : begin
- fifodata_1 <=
{round_4(ch_3_buff0),round_4(ch_2_buff0),round_4(ch_1_buff0),round_4(ch_0_buff0)};
- fifodata_2 <=
{round_4(ch_7_buff0),round_4(ch_6_buff0),round_4(ch_5_buff0),round_4(ch_4_buff0)};
- end
- 5'd2 : fifodata_1 <=
{round_2(ch_7_buff0),round_2(ch_6_buff0),round_2(ch_5_buff0),round_2(ch_4_buff0),
-
round_2(ch_3_buff0),round_2(ch_2_buff0),round_2(ch_1_buff0),round_2(ch_0_buff0)};
- 5'd1 : fifodata_1 <=
{round_1(ch_7_buff0),round_1(ch_6_buff0),round_1(ch_5_buff0),round_1(ch_4_buff0),
-
round_1(ch_3_buff0),round_1(ch_2_buff0),round_1(ch_1_buff0),round_1(ch_0_buff0),
-
round_1(ch_7_buff1),round_1(ch_6_buff1),round_1(ch_5_buff1),round_1(ch_4_buff1),
-
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1)};
- default : fifodata_1 <= 16'b0;
- endcase
- default : fifodata_1 <= 16'b0;
- endcase
+ if (buffs_ready)
+ if (bitwidth == 5'd16)
+ begin
+ fifodata_1 <= ch_0_buff0;
+ fifodata_2 <= ch_1_buff0;
+ fifodata_3 <= ch_2_buff0;
+ fifodata_4 <= ch_3_buff0;
+ fifodata_5 <= ch_4_buff0;
+ fifodata_6 <= ch_5_buff0;
+ fifodata_7 <= ch_6_buff0;
+ fifodata_8 <= ch_7_buff0;
+ end
+ else if (bitwidth == 5'd8)
+ begin
+ fifodata_1 <= {round_8(ch_1_buff0),round_8(ch_0_buff0)};
+ fifodata_2 <= {round_8(ch_3_buff0),round_8(ch_2_buff0)};
+ fifodata_3 <= {round_8(ch_5_buff0),round_8(ch_4_buff0)};
+ fifodata_4 <= {round_8(ch_7_buff0),round_8(ch_6_buff0)};
+ end
+ else
+ case(channels)
+ 4'd2 :
+ case(bitwidth)
+ 5'd4 : fifodata_1 <=
{round_4(ch_1_buff0),round_4(ch_0_buff0),round_4(ch_1_buff1),round_4(ch_0_buff1)};
+ 5'd2 : fifodata_1 <=
{round_2(ch_1_buff0),round_2(ch_0_buff0),round_2(ch_1_buff1),round_2(ch_0_buff1),
+
round_2(ch_1_buff2),round_2(ch_0_buff2),round_2(ch_1_buff3),round_2(ch_0_buff3)};
+ 5'd1 : fifodata_1 <=
{round_1(ch_1_buff0),round_1(ch_0_buff0),round_1(ch_1_buff1),round_1(ch_0_buff1),
+
round_1(ch_1_buff2),round_1(ch_0_buff2),round_1(ch_1_buff3),round_1(ch_0_buff3),
+
round_1(ch_1_buff4),round_1(ch_0_buff4),round_1(ch_1_buff5),round_1(ch_0_buff5),
+
round_1(ch_1_buff6),round_1(ch_0_buff6),round_1(ch_1_buff7),round_1(ch_0_buff7)};
+ default: fifodata_1 <= 16'b0;
+ endcase
+ 4'd4 :
+ case(bitwidth)
+ 5'd4 : fifodata_1 <=
{round_4(ch_3_buff0),round_4(ch_2_buff0),round_4(ch_1_buff0),round_4(ch_0_buff0)};
+ 5'd2 : fifodata_1 <=
{round_2(ch_3_buff0),round_2(ch_2_buff0),round_2(ch_1_buff0),round_2(ch_0_buff0),
+
round_2(ch_3_buff1),round_2(ch_2_buff1),round_2(ch_1_buff1),round_2(ch_0_buff1)};
+ 5'd1 : fifodata_1 <=
{round_1(ch_3_buff0),round_1(ch_2_buff0),round_1(ch_1_buff0),round_1(ch_0_buff0),
+
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1),
+
round_1(ch_3_buff2),round_1(ch_2_buff2),round_1(ch_1_buff2),round_1(ch_0_buff2),
+
round_1(ch_3_buff3),round_1(ch_2_buff3),round_1(ch_1_buff3),round_1(ch_0_buff3)};
+ default : fifodata_1 <= 16'b0;
+ endcase
+ 4'd6 :
+ case(bitwidth)
+ 5'd4 :
+ case(read_phase)
+ 2'd1 : fifodata_1 <=
{round_4(ch_3_buff0),round_4(ch_2_buff0),round_4(ch_1_buff0),round_4(ch_0_buff0)};
+ 2'd2 : begin
+ fifodata_1 <=
{round_4(ch_1_buff0),round_4(ch_0_buff0),round_4(ch_5_buff1),round_4(ch_4_buff1)};
+ fifodata_2 <=
{round_4(ch_5_buff0),round_4(ch_4_buff0),round_4(ch_3_buff0),round_4(ch_2_buff0)};
+ end
+ default : fifodata_1 <= 16'b0;
+ endcase
+ 5'd2 :
+ case(read_phase)
+ 2'd1 : fifodata_1 <=
{round_2(ch_1_buff0),round_2(ch_0_buff0),round_2(ch_5_buff1),round_2(ch_4_buff1),
+
round_2(ch_3_buff1),round_2(ch_2_buff1),round_2(ch_1_buff1),round_2(ch_0_buff1)};
+ 2'd2 : fifodata_1 <=
{round_2(ch_3_buff0),round_2(ch_2_buff0),round_2(ch_1_buff0),round_2(ch_0_buff0),
+
round_2(ch_5_buff1),round_2(ch_4_buff1),round_2(ch_3_buff1),round_2(ch_2_buff1)};
+ 2'd3 : fifodata_1 <=
{round_2(ch_5_buff0),round_2(ch_4_buff0),round_2(ch_3_buff0),round_2(ch_2_buff0),
+
round_2(ch_1_buff0),round_2(ch_0_buff0),round_2(ch_5_buff1),round_2(ch_4_buff1)};
+ default : fifodata_1 <= 16'b0;
+ endcase
+ 5'd1 :
+ case(read_phase)
+ 2'd1 : fifodata_1 <=
{round_1(ch_3_buff0),round_1(ch_2_buff0),round_1(ch_1_buff0),round_1(ch_0_buff0),
+
round_1(ch_5_buff1),round_1(ch_4_buff1),round_1(ch_3_buff1),round_1(ch_2_buff1),
+
round_1(ch_1_buff1),round_1(ch_0_buff1),round_1(ch_5_buff2),round_1(ch_4_buff2),
+
round_1(ch_3_buff2),round_1(ch_2_buff2),round_1(ch_1_buff2),round_1(ch_0_buff2)};
+ 2'd2 : fifodata_1 <=
{round_1(ch_1_buff0),round_1(ch_0_buff0),round_1(ch_5_buff1),round_1(ch_4_buff1),
+
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1),
+
round_1(ch_5_buff2),round_1(ch_4_buff2),round_1(ch_3_buff2),round_1(ch_2_buff2),
+
round_1(ch_1_buff2),round_1(ch_0_buff2),round_1(ch_5_buff3),round_1(ch_4_buff3)};
+ 2'd3 : fifodata_1 <=
{round_1(ch_5_buff0),round_1(ch_4_buff0),round_1(ch_3_buff0),round_1(ch_2_buff0),
+
round_1(ch_1_buff0),round_1(ch_0_buff0),round_1(ch_5_buff1),round_1(ch_4_buff1),
+
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1),
+
round_1(ch_5_buff2),round_1(ch_4_buff2),round_1(ch_3_buff2),round_1(ch_2_buff2)};
+ default : fifodata_1 <= 16'b0;
+ endcase
+ default : fifodata_1 <= 16'b0;
+ endcase
+ 4'd8 :
+ case(bitwidth)
+ 5'd4 : begin
+ fifodata_1 <=
{round_4(ch_3_buff0),round_4(ch_2_buff0),round_4(ch_1_buff0),round_4(ch_0_buff0)};
+ fifodata_2 <=
{round_4(ch_7_buff0),round_4(ch_6_buff0),round_4(ch_5_buff0),round_4(ch_4_buff0)};
+ end
+ 5'd2 : fifodata_1 <=
{round_2(ch_7_buff0),round_2(ch_6_buff0),round_2(ch_5_buff0),round_2(ch_4_buff0),
+
round_2(ch_3_buff0),round_2(ch_2_buff0),round_2(ch_1_buff0),round_2(ch_0_buff0)};
+ 5'd1 : fifodata_1 <=
{round_1(ch_7_buff0),round_1(ch_6_buff0),round_1(ch_5_buff0),round_1(ch_4_buff0),
+
round_1(ch_3_buff0),round_1(ch_2_buff0),round_1(ch_1_buff0),round_1(ch_0_buff0),
+
round_1(ch_7_buff1),round_1(ch_6_buff1),round_1(ch_5_buff1),round_1(ch_4_buff1),
+
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1)};
+ default : fifodata_1 <= 16'b0;
+ endcase
+ default : fifodata_1 <= 16'b0;
+ endcase
end
// total number of writes per read phase
@@ -402,10 +413,10 @@
always @(posedge rxclk)
if (reset)
write_phase <= 0;
- else if (write_phase == 4'd0 && write_strobe)
+ else if (write_phase == 4'd0 && buffs_ready)
write_phase <= 1;
else if (write_phase >= total_writes)
- if (write_strobe)
+ if (buffs_ready)
write_phase <= 1;
else
write_phase <= 0;
@@ -414,26 +425,20 @@
else
write_phase <= 0;
- reg [3:0] phase;
- always @(posedge rxclk)
- if(reset)
- phase <= 4'd0;
- else if(phase == 0)
- begin
- if(rxstrobe)
- phase <= 4'd1;
- end
- else if(~rx_full)
- if(phase == ((bitwidth == 5'd8) ? (channels>>1) : channels))
- phase <= 4'd0;
- else
- phase <= phase + 4'd1;
-
- assign fifodata = (bitwidth == 5'd8) ? fifodata_8_old : fifodata_16;
-
- assign fifodata_8_old = {round_8(top),round_8(bottom)};
- reg [15:0] top,bottom;
-
+ always @*
+ case(write_phase)
+ 4'd1 : fifodata <= fifodata_1;
+ 4'd2 : fifodata <= fifodata_2;
+ 4'd3 : fifodata <= fifodata_3;
+ 4'd4 : fifodata <= fifodata_4;
+ 4'd5 : fifodata <= fifodata_5;
+ 4'd6 : fifodata <= fifodata_6;
+ 4'd7 : fifodata <= fifodata_7;
+ 4'd8 : fifodata <= fifodata_8;
+ default : fifodata <= 16'b0;
+ endcase
+
+
// Rounding (Quantization) functions
function [7:0] round_8;
input [15:0] in_val;
@@ -456,44 +461,7 @@
round_1 = ~in_val[15];
endfunction // round_1
- always @*
- case(phase)
- 4'd1 : begin
- bottom = ch_0_buff0;
- top = ch_1_buff0;
- end
- 4'd2 : begin
- bottom = ch_2_buff0;
- top = ch_3_buff0;
- end
- 4'd3 : begin
- bottom = ch_4_buff0;
- top = ch_5_buff0;
- end
- 4'd4 : begin
- bottom = ch_6_buff0;
- top = ch_7_buff0;
- end
- default : begin
- top = 16'hFFFF;
- bottom = 16'hFFFF;
- end
- endcase // case(phase)
-
- always @*
- case(phase)
- 4'd1 : fifodata_16 = ch_0_buff0;
- 4'd2 : fifodata_16 = ch_1_buff0;
- 4'd3 : fifodata_16 = ch_2_buff0;
- 4'd4 : fifodata_16 = ch_3_buff0;
- 4'd5 : fifodata_16 = ch_4_buff0;
- 4'd6 : fifodata_16 = ch_5_buff0;
- 4'd7 : fifodata_16 = ch_6_buff0;
- 4'd8 : fifodata_16 = ch_7_buff0;
- default : fifodata_16 = 16'hFFFF;
- endcase // case(phase)
-
// Detect overrun
reg clear_status_dsp, rx_overrun_dsp;
always @(posedge rxclk)
@@ -505,7 +473,7 @@
always @(posedge rxclk)
if(reset)
rx_overrun_dsp <= 1'b0;
- else if(rxstrobe & (phase != 0))
+ else if(buffs_ready && write_phase != 4'b0 && write_phase != total_writes)
rx_overrun_dsp <= 1'b1;
else if(clear_status_dsp)
rx_overrun_dsp <= 1'b0;
@@ -520,7 +488,7 @@
assign debugbus[2] = rxstrobe;
assign debugbus[6:3] = channels;
assign debugbus[7] = rx_full;
- assign debugbus[11:8] = phase;
+ assign debugbus[11:8] = write_phase;
assign debugbus[12] = ch0_in;
assign debugbus[13] = clear_status_dsp;
assign debugbus[14] = rx_overrun_dsp;
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