[Commit-gnuradio] r8120 - usrp2/trunk/fpga/top/u2_rev2

[matt]

Author: matt
Date: 2008-03-27 16:25:30 -0600 (Thu, 27 Mar 2008)
New Revision: 8120

Modified:
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
Log:
who knows?


Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-03-27 22:20:35 UTC (rev 
8119)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-03-27 22:25:30 UTC (rev 
8120)
@@ -21,7 +21,24 @@
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
+verilog work "../../opencores/8b10b/encode_8b10b.v"
+verilog work "../../opencores/8b10b/decode_8b10b.v"
+verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
+verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
+verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
 verilog work "../../eth/rtl/verilog/Reg_int.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
 verilog work "../../control_lib/fifo_2clock_casc.v"
 verilog work "../../control_lib/cascadefifo2.v"
 verilog work "../../control_lib/CRC16_D16.v"