[Commit-gnuradio] r8116 - usrp2/trunk/fpga/top/u2_rev2

[matt]

Author: matt
Date: 2008-03-26 00:43:27 -0600 (Wed, 26 Mar 2008)
New Revision: 8116

Modified:
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
Log:
fails timing for some reason.  Also removes eth core for some reason


Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-03-26 06:42:43 UTC (rev 
8115)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-03-26 06:43:27 UTC (rev 
8116)
@@ -1,10 +1,13 @@
+verilog work "../../control_lib/gray2bin.v"
+verilog work "../../control_lib/bin2gray.v"
 verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
 verilog work "../../control_lib/ram_2port.v"
+verilog work "../../control_lib/gray_send.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
-verilog work "../../coregen/fifo_generator_v4_1.v"
 verilog work "../../control_lib/shortfifo.v"
 verilog work "../../control_lib/longfifo.v"
+verilog work "../../control_lib/fifo_2clock.v"
 verilog work "../../sdr_lib/sign_extend.v"
 verilog work "../../sdr_lib/cordic_stage.v"
 verilog work "../../sdr_lib/cic_int_shifter.v"
@@ -18,24 +21,7 @@
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
-verilog work "../../opencores/8b10b/encode_8b10b.v"
-verilog work "../../opencores/8b10b/decode_8b10b.v"
-verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
-verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
-verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
 verilog work "../../eth/rtl/verilog/Reg_int.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
 verilog work "../../control_lib/fifo_2clock_casc.v"
 verilog work "../../control_lib/cascadefifo2.v"
 verilog work "../../control_lib/CRC16_D16.v"