[Commit-gnuradio] r8110 - in usrp2/trunk/fpga/top: . u2_rev2

[matt]

Author: matt
Date: 2008-03-24 21:04:10 -0600 (Mon, 24 Mar 2008)
New Revision: 8110

Added:
   usrp2/trunk/fpga/top/u2_rev2/
Modified:
   usrp2/trunk/fpga/top/u2_rev2/u2_fpga.ise
   usrp2/trunk/fpga/top/u2_rev2/u2_fpga_top.prj
Log:
copied over from u2_fpga


Copied: usrp2/trunk/fpga/top/u2_rev2 (from rev 8109, 
usrp2/trunk/fpga/top/u2_fpga)

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_fpga_top.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2008-03-24 21:36:27 UTC 
(rev 8109)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_fpga_top.prj        2008-03-25 03:04:10 UTC 
(rev 8110)
@@ -36,7 +36,7 @@
 verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
-verilog work "../../control_lib/ss_rcvr.v"
+verilog work "../../control_lib/fifo_2clock_casc.v"
 verilog work "../../control_lib/cascadefifo2.v"
 verilog work "../../control_lib/CRC16_D16.v"
 verilog work "../../timing/time_sender.v"