[Commit-gnuradio] r8019 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-03-13 21:44:13 -0600 (Thu, 13 Mar 2008)
New Revision: 8019

Added:
   usrp2/trunk/fpga/sdr_lib/hb_dec.v
Log:
first cut


Added: usrp2/trunk/fpga/sdr_lib/hb_dec.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_dec.v                           (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/hb_dec.v   2008-03-14 03:44:13 UTC (rev 8019)
@@ -0,0 +1,80 @@
+// Final halfband decimator 
+// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 
0 A]
+// Strobe in cannot come faster than every 2nd clock cycle
+// These taps designed by halfgen4 from ldoolittle
+
+module hb_dec
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input bypass,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     output reg stb_out,
+     output [WIDTH-1:0] data_out);
+
+   wire [3:0]          addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d, 
addr_even;
+   wire [WIDTH-1:0]    data_odd_a, data_odd_b, data_odd_c, data_odd_d, 
data_even;
+   wire [WIDTH-1:0]    sum1, sum2;     
+   reg [WIDTH-1:0]     final_sum;
+   reg [WIDTH-1:0]     coeff1, coeff2;
+
+   wire [2:0]          coeff_addr;
+   wire [35:0]                 prod1, prod2;
+   
+   always @*
+     case(coeff_addr)
+       0 : coeff1 <= 12345;
+       1 : coeff1 <= 1235;
+       2 : coeff1 <= 3456;
+       3 : coeff1 <= 345;
+       default : coeff1 <= 23456;
+     endcase // case(coeff_addr)
+   
+   always @*
+     case(coeff_addr)
+       0 : coeff2 <= 12345;
+       1 : coeff2 <= 1235;
+       2 : coeff2 <= 3456;
+       3 : coeff2 <= 345;
+       default : coeff2 <= 23456;
+     endcase // case(coeff_addr)
+   
+   srl #(.WIDTH(18)) srl_odd_a
+     
(.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_a),.out(data_odd_a));
+   srl #(.WIDTH(18)) srl_odd_b
+     
(.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_b),.out(data_odd_b));
+   srl #(.WIDTH(18)) srl_odd_c
+     
(.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_c),.out(data_odd_c));
+   srl #(.WIDTH(18)) srl_odd_d
+     
(.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_d),.out(data_odd_d));
+
+   add2_and_round_reg #(.WIDTH(18)) add1 
(.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1));
+   add2_and_round_reg #(.WIDTH(18)) add2 
(.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2));
+   
+   srl #(.WIDTH(18)) srl_even
+     
(.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even));
+
+   wire [17:0]                 final_sum_unreg;
+   
+   always @(posedge clk)
+     if(bypass)
+       final_sum <= data_in;
+     else
+       final_sum <= final_sum_unreg;
+
+   assign              data_out = final_sum;
+
+   always @(posedge clk)
+     if(rst)
+       stb_out <= 0;
+     else if(bypass)
+       stb_out <= stb_in;
+     else
+       stb_out <= 0;
+ 
+   MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), 
.B(sum1) );
+   MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), 
.B(sum2) );
+   add2_and_round_reg #(.WIDTH(18)) add3 
(.clk(clk),.in1(prod1[35:18]),.in2(prod2[35:18]),.sum(final_sum_unreg));
+ 
+endmodule // hb_dec