[Commit-gnuradio] r8004 - usrp2/trunk/fpga/serdes

[matt]

Author: matt
Date: 2008-03-12 13:17:55 -0600 (Wed, 12 Mar 2008)
New Revision: 8004

Modified:
   usrp2/trunk/fpga/serdes/serdes_rx.v
Log:
change logic for detecting xon/xoff, switch to xilinx async fifo


Modified: usrp2/trunk/fpga/serdes/serdes_rx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_rx.v 2008-03-12 19:16:38 UTC (rev 8003)
+++ usrp2/trunk/fpga/serdes/serdes_rx.v 2008-03-12 19:17:55 UTC (rev 8004)
@@ -102,8 +102,8 @@
    
    assign      chosen_data = odd ? odd_data : even_data;
 
-   assign      xon_rcvd = (chosen_data == {2'b11,K_XON,K_XON});
-   assign      xoff_rcvd = (chosen_data == {2'b11,K_XOFF,K_XOFF});
+   assign      xon_rcvd = ({1'b1,K_XON} == {ser_rkmsb,ser_r[15:8]}) | 
({1'b1,K_XON} == {ser_rklsb,ser_r[7:0]} );
+   assign      xoff_rcvd = ({1'b1,K_XOFF} == {ser_rkmsb,ser_r[15:8]}) | 
({1'b1,K_XOFF} == {ser_rklsb,ser_r[7:0]} );
 
    wire        wait_here = ((chosen_data == {2'b11,K_COMMA,K_COMMA})||
                            (chosen_data == {2'b11,K_XON,K_XON})||
@@ -261,12 +261,26 @@
       .fifo_space(fifo_space) );
 */
    wire [FIFOSIZE-1:0] level;
-   fifo_2clock #(.DWIDTH(35),.AWIDTH(FIFOSIZE)) serdes_rx_fifo
+/*
+    fifo_2clock #(.DWIDTH(35),.AWIDTH(FIFOSIZE)) serdes_rx_fifo
      (.arst(rst),
       .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), .write(write), 
.full(full),
       .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), .read(read), 
.empty(empty),
       .level_rclk(level) );
-
+*/
+   fifo_generator_v4_1 ser_rx_fifo
+     (.din({error_i,sop_i,eop_i,line_i}),
+      .rd_clk(clk),
+      .rd_en(read),
+      .rst(rst),
+      .wr_clk(ser_rx_clk),
+      .wr_en(write),
+      .dout({error_o,sop_o,eop_o,line_o}),
+      .empty(empty),
+      .full(full),
+      .rd_data_count(),
+      .wr_data_count(level));
+   
    assign             fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - 
                       {{(16-FIFOSIZE){1'b0}},level};