[Commit-gnuradio] r8002 - usrp2/trunk/firmware/apps

[matt]

Author: matt
Date: 2008-03-12 13:14:48 -0600 (Wed, 12 Mar 2008)
New Revision: 8002

Modified:
   usrp2/trunk/firmware/apps/sd_bounce.c
   usrp2/trunk/firmware/apps/sd_gentest.c
Log:
proper reference locking


Modified: usrp2/trunk/firmware/apps/sd_bounce.c
===================================================================
--- usrp2/trunk/firmware/apps/sd_bounce.c       2008-03-12 18:26:22 UTC (rev 
8001)
+++ usrp2/trunk/firmware/apps/sd_bounce.c       2008-03-12 19:14:48 UTC (rev 
8002)
@@ -30,6 +30,7 @@
 #include <stddef.h>
 #include <stdlib.h>
 #include <string.h>
+#include <ad9510.h>
 
 // ----------------------------------------------------------------
 
@@ -97,6 +98,19 @@
 {
   u2_init();
 
+  // Get our clock from the mimo interface
+
+  // if(I WANT TO LOCK TO A REFERENCE CLOCK) 
+  // Reg 8, Charge pump on, dig lock det, positive PFD, 47
+  ad9510_write_reg(0x08, 0x47);
+  ad9510_write_reg(0x5A, 0x01); // Update Regs
+  // if (LOCK_TO_MIMO_REF)
+
+  // Turn on ref output and choose the MIMO connector
+  output_regs->clk_ctrl = 0x15;
+  // Turn on ref output and choose the SMA connector
+  //output_regs->clk_ctrl = 0x14;
+
   // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
   hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_0);
   hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_0);

Modified: usrp2/trunk/firmware/apps/sd_gentest.c
===================================================================
--- usrp2/trunk/firmware/apps/sd_gentest.c      2008-03-12 18:26:22 UTC (rev 
8001)
+++ usrp2/trunk/firmware/apps/sd_gentest.c      2008-03-12 19:14:48 UTC (rev 
8002)
@@ -30,6 +30,7 @@
 #include <stddef.h>
 #include <stdlib.h>
 #include <string.h>
+#include <ad9510.h>
 
 // ----------------------------------------------------------------
 
@@ -97,6 +98,20 @@
 {
   u2_init();
 
+
+  // Reg 8, Charge pump on, dig lock det, positive PFD, 47
+  ad9510_write_reg(0x08, 0x47);
+  // turn on ref input and choose the SMA
+  output_regs->clk_ctrl = 0x14; 
+
+  // provide a clock for the serdes (THEY_LOCK_TO_ME)
+  ad9510_write_reg(0x3E, 0x00); // Turn on output 2 (clk_exp_out), normal 
levels
+  ad9510_write_reg(0x4D, 0x00); // Turn on Div2
+  ad9510_write_reg(0x4C, 0x44); // Set Div2 = 10, output a 10 MHz clock
+  ad9510_write_reg(0x5A, 0x01); // Update Regs
+
+
+
   // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
   hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_0);
   hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_0);