[Commit-gnuradio] r7966 - usrp2/trunk/fpga/serdes

[matt]

Author: matt
Date: 2008-03-07 20:09:14 -0700 (Fri, 07 Mar 2008)
New Revision: 7966

Modified:
   usrp2/trunk/fpga/serdes/serdes_rx.v
Log:
take a shot at moving the bulk of the rx serdes processing to the ser_rx_clk 
domain, get rid of ss_rcvr


Modified: usrp2/trunk/fpga/serdes/serdes_rx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_rx.v 2008-03-08 03:04:14 UTC (rev 7965)
+++ usrp2/trunk/fpga/serdes/serdes_rx.v 2008-03-08 03:09:14 UTC (rev 7966)
@@ -79,19 +79,22 @@
    reg [15:0]  CRC;
    wire [15:0] nextCRC;
    reg                write_d;
-   
+
+   /*
    ss_rcvr #(.WIDTH(18)) ss_rcvr
      (.rxclk(ser_rx_clk),.sysclk(clk),.rst(rst),
       .data_in({ser_rkmsb,ser_rklsb,ser_r}),.data_out(even_data),
       .clock_present());
+   */
+   assign      even_data = {ser_rkmsb,ser_rklsb,ser_r};
    
-   always @(posedge clk)
+   always @(posedge ser_rx_clk)
      if(rst)
        holder <= 9'd0;
      else
        holder <= {even_data[17],even_data[15:8]};
    
-   always @(posedge clk)
+   always @(posedge ser_rx_clk)
      if(rst)
        odd_data <= 18'd0;
      else
@@ -106,13 +109,13 @@
                            (chosen_data == {2'b11,K_XON,K_XON})||
                            (chosen_data == {2'b11,K_XOFF,K_XOFF}) );
 
-   always @(posedge clk)
+   always @(posedge ser_rx_clk)
      if(rst) sop_i <= 0;
      else if(state == FIRSTLINE1) sop_i <= 1;
      else if(write_d) sop_i <= 0;
    
    reg                write_pre;
-   always @(posedge clk)
+   always @(posedge ser_rx_clk)
      if(rst)
        begin
          state <= IDLE;
@@ -233,7 +236,7 @@
        endcase // case(state)
    
    
-   always @(posedge clk)
+   always @(posedge ser_rx_clk)
      if(rst)
        CRC <= 16'hFFFF;
      else if(state == IDLE)
@@ -243,17 +246,29 @@
 
    CRC16_D16 crc_blk(chosen_data[15:0],CRC,nextCRC);
 
-   always @(posedge clk)
+   always @(posedge ser_rx_clk)
      if(rst) write_d <= 0;
      else write_d <= write_pre;
 
    // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes
    assign write = eop_i | (error_i & ~full) | (write_d & (state != CRC_CHECK));
+
+/*   
    cascadefifo2 #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
      (.clk(clk),.rst(rst),.clear(0),
       .datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
       .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty),
       .fifo_space(fifo_space) );
+*/
+   wire [FIFOSIZE-1:0] level;
+   fifo_2clock #(.DWIDTH(35),.AWIDTH(FIFOSIZE)) serdes_rx_fifo
+     (.arst(rst),
+      .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), .write(write), 
.full(full),
+      .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), .read(read), 
.empty(empty),
+      .level_rclk(level) );
+
+   assign             fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - 
+                      {{(16-FIFOSIZE){1'b0}},level};
    
    // Internal FIFO to Buffer interface
    reg                xfer_active;