[Commit-gnuradio] r7311 - usrp2/trunk/firmware/lib

[matt]

Author: matt
Date: 2007-12-30 16:59:05 -0700 (Sun, 30 Dec 2007)
New Revision: 7311

Modified:
   usrp2/trunk/firmware/lib/u2_init.c
Log:
demonstrated time and freq sync capability.  This needs to be cleaned up so 
options can be set from firmware


Modified: usrp2/trunk/firmware/lib/u2_init.c
===================================================================
--- usrp2/trunk/firmware/lib/u2_init.c  2007-12-30 23:57:38 UTC (rev 7310)
+++ usrp2/trunk/firmware/lib/u2_init.c  2007-12-30 23:59:05 UTC (rev 7311)
@@ -46,7 +46,7 @@
   // init spi, so that we can switch over to the high-speed clock
   spi_init();
 
-  // Set up AD9510
+  // Set up basic clocking functions in AD9510
   spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00004500, 24, 0); // CLK2 drives 
distribution
   spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00003D00, 24, 0); // Turn on 
output 1 (FPGA CLK), normal levels
   spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00004B80, 24, 0); // Bypass 
divider 1
@@ -54,13 +54,72 @@
 
   spi_wait();
 
+  // Set up PLL for 10 MHz reference
+  // Reg 4, A counter, Don't Care
+  // Reg 5, B counter MSBs, 0
+  spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00000500, 24, 0);
+  // Reg 6, B counter LSBs, 5
+  spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00000605, 24, 0);
+  // Reg 7, Loss of reference detect, doesn't work yet, 0
+
+#define LOCK_TO_EXT_REF 0
+#define LOCK_TO_MIMO_REF 1
+#define LOCK_NONE 0
+#define THEY_LOCK_TO_ME 0
+
+  volatile int *pps_ctrl = 0xF800;
+  *pps_ctrl = 4;
+
+  // if(I WANT TO LOCK TO A REFERENCE CLOCK) 
+  if(LOCK_TO_EXT_REF || LOCK_TO_MIMO_REF) {
+    // Reg 8, Charge pump on, dig lock det, positive PFD, 47
+    spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00000847, 24, 0);
+  }
+  else {
+    // Reg 8, Charge pump off, dig lock det, positive PFD, 47
+    spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00000800, 24, 0);
+  }
+  
+  // Reg 9, Charge pump current, 3mA, 40
+  spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00000940, 24, 0);
+  // Reg A, Prescalar of 2, everything normal 04
+  spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00000A04, 24, 0);
+  // Reg B, R Div MSBs, 0
+  spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00000B00, 24, 0);
+  // Reg C, R Div LSBs, 1
+  spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00000C01, 24, 0);
+  // Reg D, Antibacklash, Digital lock det, 0
+
+  spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00005A01, 24, 0); // Update Regs
+
+  spi_wait();
+
   // Allow for clock switchover
-  output_regs->clk_ctrl = 0x1C;
-
+  if (LOCK_NONE) {
+    // Disable both ext clk inputs
+    output_regs->clk_ctrl = 0x10;
+  }
+  else if (LOCK_TO_EXT_REF) {
+    // turn on ref output and choose the SMA
+    output_regs->clk_ctrl = 0x14; 
+  }
+  else if (LOCK_TO_MIMO_REF) {
+    // Turn on ref output and choose the MIMO connector
+    output_regs->clk_ctrl = 0x15;  
+  }
+  
   // Set up other clocks
   spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00003C02, 24, 0); // Turn off 
output 0 (unused)
-  spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00003E00, 24, 0); // Turn on 
output 2 (clk_exp_out), normal levels
-  spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00004D80, 24, 0); // Bypass 
divider 2
+  
+  if (THEY_LOCK_TO_ME) {
+    spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00003E00, 24, 0); // Turn on 
output 2 (clk_exp_out), normal levels
+    spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00004D00, 24, 0); // Turn on Div2
+    spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00004C44, 24, 0); // Set Div2 = 
10, output a 10 MHz clock
+  }
+  else {
+    spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00003E02, 24, 0); // Turn off 
output 2 (clk_exp_out)
+    spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00004D80, 24, 0); // Bypass 
divider 2
+  }
   spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00004001, 24, 0); // Turn off 
output 4 (phy_clk)
   spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00004201, 24, 0); // Turn off 
output 6 (db_tx_clk)
   spi_transact(SPI_TXONLY, SPI_SS_AD9510, 0x00004301, 24, 0); // Turn off 
output 7 (db_rx_clk)