[Commit-gnuradio] r7276 - in usrp2/trunk/fpga: testbench top/single_u2_sim

[matt]

Author: matt
Date: 2007-12-26 16:51:15 -0700 (Wed, 26 Dec 2007)
New Revision: 7276

Added:
   usrp2/trunk/fpga/testbench/BOOTSTRAP.sav
   usrp2/trunk/fpga/testbench/PAUSE.sav
   usrp2/trunk/fpga/testbench/README
   usrp2/trunk/fpga/testbench/SERDES.sav
   usrp2/trunk/fpga/testbench/U2_SIM.sav
Removed:
   usrp2/trunk/fpga/top/single_u2_sim/BOOTSTRAP.sav
   usrp2/trunk/fpga/top/single_u2_sim/README
   usrp2/trunk/fpga/top/single_u2_sim/U2_SIM.sav
Log:
moving stuff around again


Copied: usrp2/trunk/fpga/testbench/BOOTSTRAP.sav (from rev 7268, 
usrp2/trunk/fpga/top/single_u2_sim/BOOTSTRAP.sav)
===================================================================
--- usrp2/trunk/fpga/testbench/BOOTSTRAP.sav                            (rev 0)
+++ usrp2/trunk/fpga/testbench/BOOTSTRAP.sav    2007-12-26 23:51:15 UTC (rev 
7276)
@@ -0,0 +1,82 @@
+[size] 1400 971
+[pos] -1 -1
+*-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1 -1
address@hidden
+u2_sim_top.cpld_clk
+u2_sim_top.cpld_detached
+u2_sim_top.cpld_din
+u2_sim_top.cpld_done
+u2_sim_top.cpld_start
+u2_sim_top.aux_clk
+u2_sim_top.clk_fpga
+u2_sim_top.clk_sel[1:0]
+u2_sim_top.clk_en[1:0]
+u2_sim_top.u2_basic.ram_loader_rst
+u2_sim_top.u2_basic.wb_rst
+u2_sim_top.u2_basic.sysctrl.POR
+u2_sim_top.u2_basic.sysctrl.ram_loader_done_i
+u2_sim_top.cpld_model.sclk
+u2_sim_top.cpld_model.start
+u2_sim_top.u2_basic.ram_loader.rst_i
+u2_sim_top.sen_clk
+u2_sim_top.sen_dac
+u2_sim_top.sclk
address@hidden
+u2_sim_top.u2_basic.shared_spi.wb_sel_i[3:0]
+u2_sim_top.u2_basic.shared_spi.wb_adr_i[4:0]
+u2_sim_top.u2_basic.shared_spi.wb_dat_i[31:0]
address@hidden
+u2_sim_top.u2_basic.shared_spi.wb_we_i
+u2_sim_top.u2_basic.shared_spi.wb_stb_i
+u2_sim_top.u2_basic.shared_spi.wb_ack_o
address@hidden
+u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0]
+u2_sim_top.u2_basic.shared_spi.ctrl[13:0]
+u2_sim_top.u2_basic.shared_spi.divider[15:0]
+u2_sim_top.u2_basic.shared_spi.char_len[6:0]
+u2_sim_top.u2_basic.shared_spi.ss[7:0]
+u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0]
+u2_sim_top.u2_basic.shared_spi.rx[127:0]
address@hidden
+u2_sim_top.u2_basic.control_lines.wb_stb_i
+u2_sim_top.u2_basic.control_lines.wb_we_i
address@hidden
+u2_sim_top.u2_basic.control_lines.wb_dat_i[31:0]
+u2_sim_top.u2_basic.control_lines.wb_dat_o[31:0]
+u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0]
address@hidden
+u2_sim_top.u2_basic.control_lines.wb_cyc_i
address@hidden
+u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0]
address@hidden
+u2_sim_top.clock_ready
+u2_sim_top.u2_basic.ram_loader.done_o
+u2_sim_top.u2_basic.dsp_rst
+u2_sim_top.u2_basic.ram_loader_rst
+u2_sim_top.u2_basic.wb_rst
address@hidden
+u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0]
address@hidden
+u2_sim_top.u2_basic.aeMB.iwb_ack_i
+u2_sim_top.u2_basic.ram_loader_done
address@hidden
+u2_sim_top.u2_basic.iram_rd_adr[15:0]
+u2_sim_top.u2_basic.iram_rd_dat[31:0]
address@hidden
+u2_sim_top.u2_basic.iram_wr_we
+u2_sim_top.u2_basic.iram_wr_stb
address@hidden
+u2_sim_top.u2_basic.iram_wr_sel[3:0]
+u2_sim_top.u2_basic.iram_wr_dat[31:0]
+u2_sim_top.u2_basic.iram_wr_adr[15:0]
address@hidden
+u2_sim_top.u2_basic.ram_loader.ram_loader_done_o
+u2_sim_top.u2_basic.ID_ram.dwb_we_i
+u2_sim_top.u2_basic.ID_ram.iwb_we_i
+u2_sim_top.u2_basic.ram_loader.ram_we
+u2_sim_top.u2_basic.ram_loader.ram_we_q
+u2_sim_top.u2_basic.ram_loader.ram_we_s
+u2_sim_top.u2_basic.ram_loader.wb_ack_i
+u2_sim_top.u2_basic.ID_ram.iwb_ack_o
+u2_sim_top.u2_basic.ID_ram.iwb_stb_i
+u2_sim_top.u2_basic.ID_ram.wb_rst_i

Added: usrp2/trunk/fpga/testbench/PAUSE.sav
===================================================================
--- usrp2/trunk/fpga/testbench/PAUSE.sav                                (rev 0)
+++ usrp2/trunk/fpga/testbench/PAUSE.sav        2007-12-26 23:51:15 UTC (rev 
7276)
@@ -0,0 +1,62 @@
+[size] 1400 967
+[pos] -1 -1
+*-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] u2_sim_top.
+[treeopen] u2_sim_top.u2_basic.
+[treeopen] u2_sim_top.u2_basic.MAC_top.
+[treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx.
address@hidden
+u2_sim_top.GMII_TXD[7:0]
address@hidden
+u2_sim_top.GMII_TX_EN
address@hidden
+-
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0]
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0]
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0]
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0]
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk
address@hidden
+-
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1
address@hidden
+-
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1
address@hidden
+-
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0]
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0]
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en
+u2_sim_top.u2_basic.proc_int
address@hidden
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0]
+u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0]
address@hidden
+u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0]

Copied: usrp2/trunk/fpga/testbench/README (from rev 7268, 
usrp2/trunk/fpga/top/single_u2_sim/README)
===================================================================
--- usrp2/trunk/fpga/testbench/README                           (rev 0)
+++ usrp2/trunk/fpga/testbench/README   2007-12-26 23:51:15 UTC (rev 7276)
@@ -0,0 +1,5 @@
+The path to happiness:
+
+make clean
+make
+./u2_sim +rom=../../firmware/eth_test.rom -lxt2

Added: usrp2/trunk/fpga/testbench/SERDES.sav
===================================================================
--- usrp2/trunk/fpga/testbench/SERDES.sav                               (rev 0)
+++ usrp2/trunk/fpga/testbench/SERDES.sav       2007-12-26 23:51:15 UTC (rev 
7276)
@@ -0,0 +1,35 @@
+[size] 1400 967
+[pos] -1 -1
+*-30.885946 6591910000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] u2_sim_top.
+[treeopen] u2_sim_top.u2_basic.
+[treeopen] u2_sim_top.u2_basic.serdes.
address@hidden
+u2_sim_top.u2_basic.serdes.ser_t[15:0]
address@hidden
+u2_sim_top.u2_basic.serdes.ser_tklsb
+u2_sim_top.u2_basic.serdes.ser_tkmsb
+u2_sim_top.u2_basic.ram_loader.ram_loader_done_o
+u2_sim_top.u2_basic.proc_int
address@hidden
+u2_sim_top.u2_basic.serdes.fifo_space[15:0]
address@hidden
+u2_sim_top.u2_basic.serdes.inhibit_tx
+u2_sim_top.u2_basic.serdes.send_xoff
+u2_sim_top.u2_basic.serdes.send_xon
+u2_sim_top.u2_basic.serdes.sent
+u2_sim_top.u2_basic.serdes.xoff_rcvd
+u2_sim_top.u2_basic.serdes.xon_rcvd
+u2_sim_top.u2_basic.serdes.serdes_rx.wr_write_o
+u2_sim_top.u2_basic.serdes.serdes_rx.wr_done_o
+u2_sim_top.u2_basic.serdes.serdes_rx.write
address@hidden
+u2_sim_top.u2_basic.serdes.serdes_rx.line_i[31:0]
address@hidden
+(0)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0]
+(1)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0]
address@hidden
+#chosen_data[15:0] (2)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(3)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(4)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(5)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(6)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(7)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(8)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(9)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(10)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(11)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(12)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(13)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(14)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(15)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(16)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] 
(17)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0]
+u2_sim_top.u2_basic.serdes.ser_t[15:0]
address@hidden
+u2_sim_top.u2_basic.serdes.ser_tklsb

Copied: usrp2/trunk/fpga/testbench/U2_SIM.sav (from rev 7268, 
usrp2/trunk/fpga/top/single_u2_sim/U2_SIM.sav)
===================================================================
--- usrp2/trunk/fpga/testbench/U2_SIM.sav                               (rev 0)
+++ usrp2/trunk/fpga/testbench/U2_SIM.sav       2007-12-26 23:51:15 UTC (rev 
7276)
@@ -0,0 +1,95 @@
+[size] 1400 971
+[pos] -1 -1
+*-18.079937 3641000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1
address@hidden
+u2_sim_top.adc_oen_a
+u2_sim_top.adc_oen_b
+u2_sim_top.adc_pdn_a
+u2_sim_top.adc_pdn_b
+u2_sim_top.aux_clk
+u2_sim_top.POR
+u2_sim_top.clk_fpga
+u2_sim_top.clk_en[1:0]
+u2_sim_top.clk_sel[1:0]
+u2_sim_top.led1
+u2_sim_top.led2
+u2_sim_top.sclk
+u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.gnt[2:0]
+u2_sim_top.sda_pad_o
+u2_sim_top.sda_pad_oen_o
+u2_sim_top.sdi
+u2_sim_top.sdo
+u2_sim_top.sen_clk
+u2_sim_top.sen_dac
+u2_sim_top.ser_enable
+u2_sim_top.ser_loopen
+u2_sim_top.ser_prbsen
+u2_sim_top.ser_rx_en
+u2_sim_top.u2_basic.sysctrl.start
+u2_sim_top.u2_basic.sysctrl.POR
+u2_sim_top.u2_basic.done
+u2_sim_top.u2_basic.sysctrl.POR
+u2_sim_top.u2_basic.sysctrl.aux_clk
+u2_sim_top.u2_basic.sysctrl.clk_fpga
+u2_sim_top.u2_basic.sysctrl.done
+u2_sim_top.u2_basic.bus_writer.start
+u2_sim_top.u2_basic.bus_writer.done
address@hidden
+u2_sim_top.u2_basic.bus_writer.rom_addr[15:0]
+u2_sim_top.u2_basic.bus_writer.rom_data[47:0]
+u2_sim_top.u2_basic.bus_writer.state[3:0]
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_ack_i
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_adr_o[15:0]
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_clk_i
+u2_sim_top.u2_basic.bus_writer.wb_cyc_o
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_dat_o[31:0]
+u2_sim_top.u2_basic.bus_writer.wb_sel_o[3:0]
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_stb_o
+u2_sim_top.u2_basic.bus_writer.wb_we_o
+u2_sim_top.u2_basic.bus_writer.wb_rst_i
+u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.req[7:0]
+u2_sim_top.sda_pad_i
+u2_sim_top.u2_basic.wb_conbus_top.m0_cyc_i
+u2_sim_top.u2_basic.wb_conbus_top.s0_cyc_o
address@hidden
+u2_sim_top.u2_basic.wb_conbus_top.m0_adr_i[15:0]
+u2_sim_top.u2_basic.wb_conbus_top.m1_adr_i[15:0]
address@hidden
+u2_sim_top.u2_basic.wb_conbus_top.m0_stb_i
+u2_sim_top.u2_basic.wb_conbus_top.m1_stb_i
+u2_sim_top.u2_basic.wb_conbus_top.s0_stb_o
+u2_sim_top.u2_basic.wb_conbus_top.s1_stb_o
+u2_sim_top.u2_basic.wb_conbus_top.s2_stb_o
+u2_sim_top.u2_basic.wb_conbus_top.s3_stb_o
+u2_sim_top.u2_basic.wb_conbus_top.s0_ack_i
+u2_sim_top.u2_basic.control_lines.wb_cyc_i
+u2_sim_top.u2_basic.control_lines.wb_stb_i
+u2_sim_top.u2_basic.control_lines.wb_we_i
+u2_sim_top.u2_basic.control_lines.wb_ack_o
+u2_sim_top.u2_basic.s0_ack
address@hidden
+u2_sim_top.u2_basic.control_lines.internal_reg[31:0]
+u2_sim_top.u2_basic.control_lines.port_output[31:0]
address@hidden
+u2_sim_top.u2_basic.led1
+u2_sim_top.u2_basic.led2
address@hidden
+u2_sim_top.u2_basic.misc_outs[7:0]
+u2_sim_top.u2_basic.clock_outs[7:0]
+u2_sim_top.u2_basic.adc_outs[7:0]
+u2_sim_top.u2_basic.serdes_outs[7:0]
address@hidden
+u2_sim_top.u2_basic.shared_spi.miso_pad_i
+u2_sim_top.u2_basic.shared_spi.mosi_pad_o
address@hidden
+u2_sim_top.u2_basic.shared_spi.ss[7:0]
+u2_sim_top.u2_basic.shared_spi.divider[15:0]
address@hidden
+u2_sim_top.u2_basic.shared_spi.sclk_pad_o
address@hidden
+u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0]

Deleted: usrp2/trunk/fpga/top/single_u2_sim/BOOTSTRAP.sav

Deleted: usrp2/trunk/fpga/top/single_u2_sim/README

Deleted: usrp2/trunk/fpga/top/single_u2_sim/U2_SIM.sav