[Commit-gnuradio] r7274 - in usrp2/trunk/fpga/top: u2_basic u2_fpga

[matt]

Author: matt
Date: 2007-12-26 16:26:20 -0700 (Wed, 26 Dec 2007)
New Revision: 7274

Modified:
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
Log:
add in ram interface


Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-12-26 23:21:39 UTC (rev 
7273)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-12-26 23:26:20 UTC (rev 
7274)
@@ -115,6 +115,16 @@
    inout [15:0] io_tx,
    inout [15:0] io_rx,
 
+   // External RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   input RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
    // Debug stuff
    output uart_tx_o, 
    input uart_rx_i,
@@ -309,10 +319,9 @@
 
    // SPI -- Slave #2
    spi_top shared_spi
-     
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
-      
.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),
-
-      .wb_err_o(s2_err),.wb_int_o(spi_int),
+     
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+      .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int),
       
.ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
       .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
 
@@ -561,6 +570,20 @@
       
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
       
.wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
       .wr_ready_i(wr0_ready),.wr_full_i(wr0_full) );
+
+   // 
///////////////////////////////////////////////////////////////////////////////////
+   // External RAM Interface
+
+   extram_interface extram_interface
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      
.rd_dat_i(rd3_dat),.rd_read_o(rd3_read),.rd_done_o(rd3_done),.rd_error_o(rd3_error),
+      .rd_sop_i(rd3_sop),.rd_eop_i(rd3_eop),
+      
.wr_dat_o(wr3_dat),.wr_write_o(wr3_write),.wr_done_o(wr3_done),.wr_error_o(wr3_error),
+      .wr_ready_i(wr3_ready),.wr_full_i(wr3_full),
+      .RAM_D(RAM_D),.RAM_A(RAM_A),.RAM_CE1n(RAM_CE1n),.RAM_CENn(RAM_CENn),
+      .RAM_CLK(RAM_CLK),.RAM_WEn(RAM_WEn),.RAM_OEn(RAM_OEn),.RAM_LDn(RAM_LDn) 
);
+
   
    // 
/////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2007-12-26 23:21:39 UTC 
(rev 7273)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2007-12-26 23:26:20 UTC 
(rev 7274)
@@ -97,6 +97,7 @@
 verilog work "../../control_lib/ram_loader.v"
 verilog work "../../control_lib/ram_harv_cache.v"
 verilog work "../../control_lib/nsgpio.v"
+verilog work "../../control_lib/extram_interface.v"
 verilog work "../../control_lib/buffer_pool.v"
 verilog work "../../control_lib/atr_controller.v"
 verilog work "../u2_basic/u2_basic.v"

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2007-12-26 23:21:39 UTC (rev 
7273)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2007-12-26 23:26:20 UTC (rev 
7274)
@@ -41,14 +41,14 @@
    input PHY_CLK,   // possibly use on-board osc
 
    // RAM
-   input [17:0] RAM_D,
-   input [18:0] RAM_A,
-   input RAM_CE1n,
-   input RAM_CENn,
-   input RAM_CLK,
-   input RAM_WEn,
-   input RAM_OEn,
-   input RAM_LDn,
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
    
    // SERDES
    output ser_enable,
@@ -318,6 +318,14 @@
                     .sen_rx_dac        (sen_rx_dac),
                     .io_tx             (io_tx[15:0]),
                     .io_rx             (io_rx[15:0]),
+                    .RAM_D             (RAM_D),
+                    .RAM_A             (RAM_A),
+                    .RAM_CE1n          (RAM_CE1n),
+                    .RAM_CENn          (RAM_CENn),
+                    .RAM_CLK           (RAM_CLK),
+                    .RAM_WEn           (RAM_WEn),
+                    .RAM_OEn           (RAM_OEn),
+                    .RAM_LDn           (RAM_LDn), 
                     .uart_tx_o         (),
                     .uart_rx_i         (),
                     .uart_baud_o       (),