[Commit-gnuradio] r7266 - usrp2/trunk/fpga/timing

[matt]

Author: matt
Date: 2007-12-26 12:36:45 -0700 (Wed, 26 Dec 2007)
New Revision: 7266

Added:
   usrp2/trunk/fpga/timing/time_sync.v
Modified:
   usrp2/trunk/fpga/timing/time_receiver.v
   usrp2/trunk/fpga/timing/time_sender.v
   usrp2/trunk/fpga/timing/timer.v
Log:
work in progress


Modified: usrp2/trunk/fpga/timing/time_receiver.v
===================================================================
--- usrp2/trunk/fpga/timing/time_receiver.v     2007-12-26 19:29:13 UTC (rev 
7265)
+++ usrp2/trunk/fpga/timing/time_receiver.v     2007-12-26 19:36:45 UTC (rev 
7266)
@@ -2,7 +2,7 @@
 module time_receiver
   (input clk, input rst,
    output reg [31:0] master_clock,
-   output reg pps,
+   output reg sync_rcvd,
    input exp_pps_in);
 
    wire       code_err, disp_err, dispout, complete_word;
@@ -92,16 +92,16 @@
      if(rst)
        begin
          master_clock <= 0;
-         pps <= 0;
+         sync_rcvd <= 0;
        end
      else if(complete_word & (state == STATE_T3))
        begin
-         pps <= 1;
          master_clock <= {clock_a, clock_b, clock_c, dataout_reg[7:0]};
+         sync_rcvd <= 1;
        end
      else
        begin
          master_clock <= master_clock + 1;
-         pps <= 0;
+         sync_rcvd <= 0;
        end
 endmodule // time_sender

Modified: usrp2/trunk/fpga/timing/time_sender.v
===================================================================
--- usrp2/trunk/fpga/timing/time_sender.v       2007-12-26 19:29:13 UTC (rev 
7265)
+++ usrp2/trunk/fpga/timing/time_sender.v       2007-12-26 19:36:45 UTC (rev 
7266)
@@ -3,7 +3,7 @@
 module time_sender
   (input clk, input rst,
    input [31:0] master_clock,
-   input pps,
+   input send_sync,
    output exp_pps_out);
 
    reg [7:0] datain;
@@ -41,7 +41,7 @@
    always @(posedge clk)
      if(rst)
        bit_count <= 0;
-     else if(new_word | pps)
+     else if(new_word | send_sync)
        bit_count <= 0;
      else
        bit_count <= bit_count + 1;
@@ -61,7 +61,7 @@
    always @(posedge clk)
      if(rst)
        master_clock_reg <= 0;
-     else if(pps)
+     else if(send_sync)
        master_clock_reg <= master_clock;
    
    always @(posedge clk)
@@ -71,7 +71,7 @@
          state <= SEND_IDLE;
        end
      else
-       if(pps)
+       if(send_sync)
         state <= SEND_HEAD;
        else if(new_word)
         case(state)

Added: usrp2/trunk/fpga/timing/time_sync.v
===================================================================
--- usrp2/trunk/fpga/timing/time_sync.v                         (rev 0)
+++ usrp2/trunk/fpga/timing/time_sync.v 2007-12-26 19:36:45 UTC (rev 7266)
@@ -0,0 +1,105 @@
+
+
+module time_sync
+  (input wb_clk_i, input rst_i,
+   input cyc_i, input stb_i, input [2:0] adr_i,
+   input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
+   input sys_clk_i, output [31:0] master_time_o,
+   input pps_in, input exp_pps_in, output reg exp_pps_out,
+   output int_o );
+
+   // Generate Internal master time if we are the master
+   reg [31:0] master_time;
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       master_time <= 0;
+     else
+       master_time <= master_time + 1;
+   assign     master_time_o = master_time;
+
+   time_sender time_sender
+     (.clk(clk),.rst(rst),
+      .master_clock(master_clock),
+      .send_sync(send_sync),
+      .exp_pps_out(exp_pps) );
+
+   time_receiver time_receiver
+     (.clk(clk),.rst(rst),
+      .master_clock(master_clock_rcv),
+      .sync_rcvd(sync_rcvd),
+      .exp_pps_in(exp_pps) );
+
+
+   
+   reg [31:0] pps_time, pps_time_wb;
+   reg [1:0]  pps_source;
+   reg               pps_in_d1, pps_in_d2;
+   wire       pps_free_run;
+   reg               pps_int_enable;
+   reg               exp_pps_in_decoded;
+   
+   assign     ack_o = stb_i;
+
+   always @(posedge wb_clk_i)
+     if(rst_i)
+       begin
+         pps_source <= 0;
+         pps_int_enable <= 0;
+       end
+     else if(stb_i & we_i)
+       begin
+         pps_source <= dat_i[1:0];
+         pps_int_enable <= dat_i[2];
+       end
+   
+   always @(posedge sys_clk_i)
+     if(pps_internal)
+       pps_time <= master_time;
+
+   always @(posedge wb_clk_i)
+     pps_time_wb <= pps_time;
+   
+   assign dat_o = pps_time;
+   assign int_o = pps_int_enable & pps_internal;
+
+   assign pps_internal = 
+         (pps_source == 1) ? pps_ext :
+         (pps_source == 2) ? exp_pps_in_decoded :
+         pps_free_run;
+
+   // Generate internal free-runnning PPS clock
+   localparam ONE_SECOND = 100000000-1;  // 100 million minus 1
+   reg [31:0] counter;
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       counter <= 0;
+     else if(counter == ONE_SECOND)
+       counter <= 0;
+     else
+       counter <= counter + 1;
+   assign pps_free_run = (counter == ONE_SECOND);
+   
+   // Decode Expansion PPS Input
+   reg           exp_pps_in_d1;
+   always @(posedge sys_clk_i) 
+     begin
+       exp_pps_in_d1 <= exp_pps_in;
+       exp_pps_in_decoded <= (exp_pps_in_d1 == exp_pps_in);
+     end
+   
+   // Encode Expansion PPS Output
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       exp_pps_out <= 0;
+     else if(~pps_internal)
+       exp_pps_out <= ~exp_pps_out;
+
+   // Properly Latch and edge detect External PPS input
+   always @(posedge sys_clk_i)
+     begin
+       pps_in_d1 <= pps_in;
+       pps_in_d2 <= pps_in_d1;
+     end
+   assign pps_ext = pps_in_d1 & ~pps_in_d2;
+   
+endmodule // time_sync

Modified: usrp2/trunk/fpga/timing/timer.v
===================================================================
--- usrp2/trunk/fpga/timing/timer.v     2007-12-26 19:29:13 UTC (rev 7265)
+++ usrp2/trunk/fpga/timing/timer.v     2007-12-26 19:36:45 UTC (rev 7266)
@@ -4,21 +4,12 @@
   (input wb_clk_i, input rst_i,
    input cyc_i, input stb_i, input [2:0] adr_i,
    input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
-   input sys_clk_i, output [31:0] master_time_o,
+   input sys_clk_i, input [31:0] master_time_i,
    output int_o );
-   
 
-   reg [31:0] master_time;
-   always @(posedge sys_clk_i)
-     if(rst_i)
-       master_time <= 0;
-     else
-       master_time <= master_time + 1;
-   assign     master_time_o = master_time;
-
    reg [31:0] time_wb;
    always @(posedge wb_clk_i)
-     time_wb <= master_time;
+     time_wb <= master_time_i;
 
    assign     ack_o = stb_i;
 
@@ -31,7 +22,7 @@
          int_time <= 0;
          int_reg <= 0;
        end
-     else if(|int_time && (master_time == int_time))
+     else if(|int_time && (master_time_i == int_time))
        begin
          int_time <= 0;
          int_reg <= 1;