[Commit-gnuradio] r7256 - usrp2/trunk/fpga/timing

[matt]

Author: matt
Date: 2007-12-24 12:10:23 -0700 (Mon, 24 Dec 2007)
New Revision: 7256

Modified:
   usrp2/trunk/fpga/timing/pps.v
Log:
first cut at pps block, needs a lot of discussion


Modified: usrp2/trunk/fpga/timing/pps.v
===================================================================
--- usrp2/trunk/fpga/timing/pps.v       2007-12-24 15:08:41 UTC (rev 7255)
+++ usrp2/trunk/fpga/timing/pps.v       2007-12-24 19:10:23 UTC (rev 7256)
@@ -1,26 +1,82 @@
 
 
 module pps
-  (input clk, input rst,
-   input pps_in,
-   input exp_pps_in,
-   output exp_pps_out,
-   input [31:0] master_time
-   );
+  (input wb_clk_i, input rst_i,
+   input cyc_i, input stb_i, input [2:0] adr_i,
+   input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
+   input sys_clk_i, input [31:0] master_time,
+   input pps_in, input exp_pps_in, output reg exp_pps_out,
+   output int_o );
 
-   localparam  MAX = 14;
+   reg [31:0] pps_time, pps_time_wb;
+   reg [1:0]  pps_source;
+   reg               pps_in_d1, pps_in_d2;
+   wire       pps_free_run;
+   reg               pps_int_enable;
+   reg               exp_pps_in_decoded;
    
-   reg [7:0]   counter;
-   always @(posedge clk)
-     if(rst)
+   assign     ack_o = stb_i;
+
+   always @(posedge wb_clk_i)
+     if(rst_i)
+       begin
+         pps_source <= 0;
+         pps_int_enable <= 0;
+       end
+     else if(stb_i & we_i)
+       begin
+         pps_source <= dat_i[1:0];
+         pps_int_enable <= dat_i[2];
+       end
+   
+   always @(posedge sys_clk_i)
+     if(pps_internal)
+       pps_time <= master_time;
+
+   always @(posedge wb_clk_i)
+     pps_time_wb <= pps_time;
+   
+   assign dat_o = pps_time;
+   assign int_o = pps_int_enable & pps_internal;
+
+   assign pps_internal = 
+         (pps_source == 1) ? pps_ext :
+         (pps_source == 2) ? exp_pps_in_decoded :
+         pps_free_run;
+
+   // Generate internal free-runnning PPS clock
+   localparam ONE_SECOND = 100000000-1;  // 100 million minus 1
+   reg [31:0] counter;
+   always @(posedge sys_clk_i)
+     if(rst_i)
        counter <= 0;
-     else if(counter == MAX)
+     else if(counter == ONE_SECOND)
        counter <= 0;
      else
        counter <= counter + 1;
+   assign pps_free_run = (counter == ONE_SECOND);
+   
+   // Decode Expansion PPS Input
+   reg           exp_pps_in_d1;
+   always @(posedge sys_clk_i) 
+     begin
+       exp_pps_in_d1 <= exp_pps_in;
+       exp_pps_in_decoded <= (exp_pps_in_d1 == exp_pps_in);
+     end
+   
+   // Encode Expansion PPS Output
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       exp_pps_out <= 0;
+     else if(~pps_internal)
+       exp_pps_out <= ~exp_pps_out;
 
-   assign      exp_pps_out = counter[0];
+   // Properly Latch and edge detect External PPS input
+   always @(posedge sys_clk_i)
+     begin
+       pps_in_d1 <= pps_in;
+       pps_in_d2 <= pps_in_d1;
+     end
+   assign pps_ext = pps_in_d1 & ~pps_in_d2;
    
 endmodule // pps
-
-